Isolation of bulk FET devices with embedded stressors

Patent metadata

Field	Value
Publication number	US-9761722-B1
Application number	US-201615191608-A
Country	US
Kind code	B1
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A field-effect transistor device and a method of isolating a field-effect transistor device. The method includes forming a layer of silicon germanium (SiGe) over a substrate, and fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe. Etching the silicon layer defines a channel region below the dummy gate stack. The channel is isolated from the substrate by forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack. The cavity is filled with an oxide and a low K spacer material to isolate the channel region from the substrate.

First claim

What is claimed is:

1. A method of isolating a field-effect transistor (FET) device, the method comprising:
forming a layer of silicon germanium (SiGe) over a substrate;
fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe;
etching the silicon layer to define a channel region below the dummy gate stack;
forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack; and
filling the cavity with an oxide and a low K spacer material to isolate the channel region from the substrate.

2. The method of isolating the FET device according to claim 1 , further comprising depositing oxide and silicon nitride (SiN).

3. The method of isolating the FET device according to claim 1 , wherein the depositing the oxide is performed conformally, and the depositing the SiN is followed by a reactive ion etching process to shape spacers adjacent to the oxide covering the dummy gate stack.

4. The method of isolating the FET device according to claim 3 , further comprising selectively etching the spacers adjacent to the oxide covering the dummy gate stack following the forming the cavity.

5. The method of isolating the FET device according to claim 1 , wherein the etching the silicon layer to define the channel region includes partially etching the layer of SiGe.

6. The method of isolating the FET device according to claim 5 , wherein the forming the cavity includes selectively etching a remainder of the layer of SiGe.

7. The method of isolating the FET device according to claim 6 , wherein the selectively etching includes using hydrochloric acid as an etchant.

8. The method of isolating the FET device according to claim 1 , wherein the filling the cavity includes performing an oxide etch after depositing the oxide to leave peripheral portions of the cavity as unfilled notches.

9. The method of isolating the FET device according to claim 8 , wherein the filling the cavity includes filling the unfilled notches with the low K spacer material.

10. The method of isolating the FET device according to claim 8 , wherein the performing the oxide etch includes performing an isotropic etch with an over etch.

11. The method of isolating the FET device according to claim 1 , further comprising fabricating a stressor adjacent to the channel region on the substrate.

12. The method of isolating the FET device according to claim 11 , wherein the fabricating the stressor includes epitaxially growing an undoped portion of the stressor on the substrate, wherein the epitaxially growing the undoped portion includes selecting a height of the undoped portion.

13. The method of isolating the FET device according to claim 12 , wherein the fabricating the stressor includes epitaxially growing and in-situ doping a doped portion of the stressor on the undoped portion.

14. A field-effect transistor (FET) device, comprising:
a substrate;
a channel region formed as a fin between a source region and a drain region on the substrate;
a gate stack formed above the channel region, wherein the channel region is isolated from the substrate by an oxide and a low K spacer material; and
a stressor formed on the substrate adjacent to the channel region, wherein the stressor includes an undoped portion on the substrate.

15. The FET device according to claim 14 , wherein the oxide is between the low K spacer material.

16. The FET device according to claim 14 , wherein the undoped portion is silicon germanium based on the device being a p-type FET device and the undoped portion being silicon or silicon germanium based on the device being an n-type FET device.

17. The FET device according to claim 14 , wherein the stressor includes a doped portion above the undoped portion.

18. The FET device according to claim 17 , wherein the doped portion is boron-doped silicon germanium based on the device being a p-type FET device and the doped portion is phosphorous-doped silicon or arsenic-doped silicon based on the device being an n-type FET device.

Assignees

• IBM

Inventors

• Jagannathan Hemanth
• Loubet Nicolas J

Classifications

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic