S/D connection to individual channel layers in a nanosheet FET

Patent metadata

Field	Value
Publication number	US-9653287-B2
Application number	US-201514919634-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Oct 30, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer.

First claim

What is claimed is:

1. A method to form a semiconductor device, the method comprising:
forming a nanosheet layer/sacrificial layer stack comprising at least one nanosheet layer/sacrificial layer pair, each nanosheet layer/sacrificial layer pair comprising a top surface, a bottom surface, a first end surface and a second end surface, the top surface of the pair being opposite the bottom surface and the first end surface of the pair being opposite the second end surface, the nanosheet layer being on one side of the pair and the sacrificial layer being on an opposing side of the pair, the nanosheet layer comprising a first thickness at the first end surface of the pair, the sacrificial layer comprising a second thickness at the first end surface of the pair, and the first thickness and the second thicknesses both being measured in a direction that is between the top surface and the bottom surface of the pair;
removing a predetermined amount of the sacrificial layer from the first end surface of the sacrificial layer of at least one pair to form a first space associated with the pair;
forming a low-k dielectric material in each first space so that a surface of the low-k dielectric material proximate to the first end surface of the pair is in substantial alignment with the first end surface of the nanosheet layer;
forming a first conductive material layer comprising a first surface and a second surface, the first surface of the first conductive material layer being formed on the first end surface of the each pair of the stack, and the second surface of the first conductive material layer being opposite the first surface of the first conductive material layer; and
forming a source/drain contact on the second surface of the first conductive material layer.

2. The method according to claim 1 , further comprising before forming the source/drain contact on the second surface of the first conductive material layer, forming a second conductive material layer comprising a first surface and a second surface, the first surface of the second conductive material layer being formed on the second surface of the first conductive material layer, and
wherein forming the source/drain contact on the second surface of the first conductive material layer comprises forming the source/drain contact on the second surface of the second conductive material layer.

3. The method according to claim 2 , further comprising reacting the second conductive material layer with the first conductive material layer to form a salicide.

4. The method according to claim 1 , wherein the first conductive material layer is formed by deposition.

5. The method according to claim 1 , wherein the first conductive material layer comprises a polycrystalline or an amorphous conductive material, a semiconductor material, a metallic material, or a combination thereof.

6. The method according to claim 1 , wherein the first conductive material layer comprises at least in part Ti, Co, Ni, Pt, Ta, Mo, W, a metallic nitrided alloy, or a metallic nitrided silicide.

7. The method according to claim 1 ,
wherein forming the low-k dielectric material in each first space comprises forming the low-k dielectric material so that a surface of the low-k dielectric material proximate to the first end surface of the pair is recessed toward the second end surface of the pair from the first end surface of the nanosheet layer of the pair.

8. The method according to claim 1 , wherein the semiconductor device comprises a nanosheet field effect transistor (FET) of a first conductivity type or nanosheet FET of a second conductivity type, the first conductivity type being opposite from the second conductivity type.

9. A field effect transistor (FET), comprising:
a channel region comprising a nanosheet layer/sacrificial layer stack, the nanosheet layer/sacrificial layer stack comprising at least one nanosheet layer/sacrificial layer pair, each nanosheet layer/sacrificial layer pair comprising a top surface, a bottom surface, a first end surface and a second end surface, the top surface of the pair being opposite the bottom surface and the first end surface of the pair being opposite the second end surface, the nanosheet layer being on one side of the pair and the sacrificial layer being on an opposing side of the pair, the nanosheet layer comprising a first thickness at the first end surface of the pair, the sacrificial layer comprising a second thickness at the first end surface of the pair, the first thickness and the second thicknesses both being measured in a direction that is between the top surface and the bottom surface of the pair, a portion of the sacrificial layer of at least one nanosheet layer/sacrificial layer pair further comprising a low-k dielectric material proximate to the first end surface of the pair, and a surface of the low-k dielectric material proximate to the first end surface of the pair being recessed toward the second end surface of the pair from the first end surface of the nanosheet layer;
a conductive material layer comprising a first surface and a second surface, the first surface of the conductive material layer being formed on the first end surface of each pair of the stack, and the second surface of the conductive material layer being opposite the first surface of the conductive material layer; and
a source/drain contact formed on the second surface of the conductive material layer.

10. The FET according to claim 9 , wherein the conductive material layer comprises at least in part a salicide.

11. The FET according to claim 9 , wherein the conductive layer comprises a polycrystalline or an amorphous conductive material, a semiconductor material, a metallic material, or a combination thereof.

12. The FET according to claim 9 , wherein the conductive layer comprises at least in part Ti, Co, Ni, Pt, Ta, Mo, W, a metallic nitrided alloy, or a metallic nitrided silicide.

13. The FET according to claim 9 ,
wherein a surface of the low-k dielectric material proximate to the first end surface of the pair is in substantial alignment with the first end surface of the nanosheet layer.

14. A field effect transistor (FET), comprising:
a first source/drain (S/D) region;
a second S/D region; and
a channel region disposed between the first S/D region and the second S/D region, the channel region comprising:
a plurality of nanosheet layer/sacrificial layer pairs formed on each other, each nanosheet layer/sacrificial layer pair comprising:
a top surface, a bottom surface, a first end surface and a second end surface, the top surface being opposite the bottom surface and the first end surface being opposite the second end surface, the nanosheet layer being on one side of the pair and the sacrificial layer being on an opposing side of the pair, the nanosheet layer comprising a first thickness at the first end surface of the pair and a second thickness at the second end surface of the pair, the sacrificial layer comprising a third thickness at the first end surface of the pair and a fourth thickness at the second end surface of the pair, the first, second, third and fourth thicknesses being measured in a direction that is between the top surface and the bottom surface of the pair, a portion of the sacrificial layer of at least one nanosheet layer/sacrificial layer pair further comprising a low-k dielectric material proximate to the first end surface of the pair, and a surface of the low-k dielectric material proximate to the first end of the pair being recessed toward the second end surface of the pair from the first end surface of the nanosheet layer, and
a first conductive material layer comprising a f

Assignees

• Samsung Electronics Co Ltd

Inventors

• Rodder Mark
• Hong Joon
• Kittl Jorge
• Obradovic Borna

Classifications

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P14/3462 Primary

  Nanowires · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic