Method of forming gate spacer for nanowire fet device

Patent metadata

Field	Value
Publication number	US-2018138291-A1
Application number	US-201715812263-A
Country	US
Kind code	A1
Filing date	Nov 14, 2017
Priority date	Nov 14, 2016
Publication date	May 17, 2018
Grant date	—

Abstract

A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.

First claim

What is claimed:

1 . A method of forming a gate-all-around semiconductor device, comprising:
providing a substrate having a layered fin structure thereon, the layered fin structure comprising a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material: forming a dummy gate on said replacement gate material over said layered fin structure, wherein the dummy gate having a critical dimension which extends along said length of the layered fin structure; and forming a gate structure directly under said dummy gate, said gate structure comprising a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of said dummy gate.

2 . The method of claim 1 , wherein said providing a substrate comprises providing a layered fin structure having an Si channel portion and an SiGe sacrificial portion.

3 . The method of claim 2 , wherein said Si channel portion comprises a plurality of Si layers and said SiGe sacrificial portion comprises a plurality of SiGe layers, said Si layers being alternately stacked with said SiGe layers.

4 . The method of claim 1 , wherein said forming a dummy gate comprises:
forming a layer of dummy gate material on said replacement gate material; removing a portion of the dummy gate material such that a remaining portion of the dummy gate material has opposing edges defining said dummy gate having said critical dimension.

5 . The method of claim 4 , wherein said forming a gate structure comprises using the dummy gate as a mask to anisotropically etch said replacement gate material such that opposing sidewall surfaces of the replacement gate material are aligned with said opposing edges of said dummy gate.

6 . The method of claim 5 , wherein said forming a gate structure further comprises:
isotropically etching a lateral recess into each of said opposing sidewall surfaces of the replacement gate material; and filling said lateral recess with gate spacer material.

7 . The method of claim 6 , wherein said filling said lateral recess with gate spacer material comprises:
covering the substrate with said gate spacer material; and using the dummy gate as a mask to anisotropically etch said gate spacer material, such that opposing sidewall surfaces of the gate spacer material are aligned with said opposing edges of said dummy gate.

8 . The method of claim 6 , wherein said isotropically etching comprises etching to a lateral depth equal to the intended thickness of the gate spacer.

9 . The method of claim 6 , wherein said lateral depth defines a critical dimension of said metal gate region of the gate structure.

10 . The method of claim 6 , wherein said forming a gate structure comprises using the dummy gate as a mask to anisotropically etch said layered fin structure such that opposing sidewall surfaces of the sacrificial portion and channel portion are aligned with said opposing edges of said dummy gate.

11 . The method of claim 10 , wherein said forming a gate structure further comprises:
isotropically etching a lateral recess into each of said opposing sidewall surfaces of the sacrificial portion; and filling said lateral recess with gate spacer material.

12 . The method of claim 11 , wherein said isotropically etching a lateral recess into each of said opposing sidewall surfaces of the sacrificial portion comprises etching to a lateral depth no greater than an intended thickness of said gate spacers.

13 . The method of claim 11 , wherein said filling said lateral recess with gate spacer material comprises:
covering the substrate with said gate spacer material; and using the dummy gate as a mask to anisotropically etch said gate spacer material. such that opposing sidewall surfaces of the gate spacer material are aligned with said opposing edges of said dummy gate.

14 . The method of claim 12 , wherein the intended gate spacer thickness is 30-100 angstroms.

15 . The method of claim 12 , further comprising:
removing said dummy gate; forming source-drain regions adjacent to said gate spacers; releasing a remaining portion of said sacrificial portion; and forming a multilayer gate structure in said metal gate region.

16 . A gate all around nanowire FET device comprising:
at least one nanowire having opposing ends; a gate structure comprising a metal gate region surrounding a middle portion of the at least one nanowire, and gate spacers surrounding remaining end portions of the nanowire such that opposing ends of the gate spacers are aligned with respective opposing ends of the nanowire to form opposing sidewalls of the gate structure; and source-drain regions provided on said opposing sidewalls of the gate structure.

17 . The gate all around nanowire FET device of claim 16 , wherein said at least one nanowire comprises a plurality of vertically stacked nanowires, wherein opposing ends of each nanowire are aligned with said opposing sidewalls of the gate structure.

18 . The gate all around nanowire FET device of claim 16 , wherein said at least one nanowire is made of Si.

19 . The gate all around nanowire FET device of claim 16 , wherein said at least one nanowire is made of SiGe.

20 . The semiconductor device according to claim 16 , wherein each of said gate spacers has a thickness of 30-100 angstroms.

Assignees

• Tokyo Electron Ltd

Inventors

• Smith Jeffrey
• Villiers Anton

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L21/28123

  Electricity · mapped topic