Stacked nanosheet field effect transistor device with substrate isolation

Patent metadata

Field	Value
Publication number	US-9881998-B1
Application number	US-201715422572-A
Country	US
Kind code	B1
Filing date	Feb 2, 2017
Priority date	Feb 2, 2017
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a nanosheet stack structure on a semiconductor substrate, wherein the nanosheet stack structure comprises a rare earth oxide (REO) layer formed on the semiconductor substrate and a semiconductor channel layer formed on the REO layer;
forming a dummy gate structure over the nanosheet stack structure;
forming a gate insulating spacer on vertical sidewalls of the dummy gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer;
forming a first source/drain region and a second source/drain region in contact with a respective one of the end portions of the semiconductor channel layer exposed through the gate insulating spacer, wherein at least one of the first source/drain region and the second source/drain region is formed in contact with a portion of the REO layer which extends past the gate insulating spacer;
forming an insulating layer to cover the first and second source/drain regions;
removing the dummy gate structure to form a gate recess region that exposes a portion of the nanosheet stack structure surrounded by the gate insulating spacer;
etching at least a portion of the REO layer exposed in the gate recess region to form a space between the semiconductor channel layer and the REO layer; and
forming a metal gate structure within the gate recess region;
wherein a portion of the metal gate structure is disposed in the space between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the semiconductor substrate; and
wherein said at least one of the first source/drain region and the second source/drain region, which is formed in contact with the portion of the REO layer that extends past the gate insulating spacer, is isolated from the semiconductor substrate by the REO layer.

2. The method of claim 1 , wherein forming the nanosheet stack structure on the semiconductor substrate comprises:
epitaxially growing the REO layer on the semiconductor substrate;
epitaxially growing the semiconductor channel layer on the REO layer; and
patterning the REO layer and the semiconductor channel layer to form the nanosheet stack structure.

3. The method of claim 2 , wherein patterning the REO layer and the semiconductor channel layer to form the nanosheet stack structure comprises partially recessing the REO layer so that the semiconductor substrate remains covered by a remaining portion of the REO layer.

4. The method of claim 2 , wherein patterning the REO layer and the semiconductor channel layer to form the nanosheet stack structure comprises etching the semiconductor channel layer and the REO layer down to expose a surface region of the semiconductor substrate adjacent to at least one side the nanosheet stack structure.

5. The method of claim 4 , further comprising forming an isolation layer in the exposed surface region of the semiconductor substrate adjacent to the at least one side of the nanosheet stack structure.

6. The method of claim 5 , wherein at least one of the first source/drain region and the second source/drain region is disposed on the isolation layer and isolated from the semiconductor substrate by the isolation layer.

7. The method of claim 1 , wherein the first source/drain region and the second source/drain region are formed in contact with portions of the REO layer which extend past opposing sides of the gate insulating spacer.

8. The method of claim 7 , wherein forming the first, source/drain region and the second source/drain region comprises:
epitaxially growing semiconductor material on the end portions of the semiconductor channel layer and on the extended portion of the REO layer; and
patterning the epitaxially grown semiconductor material to form first and second epitaxial source/drain regions.

9. The method of claim 1 , wherein forming the metal gate structure within the gate recess region comprises:
forming a conformal gate dielectric layer on exposed surfaces of the semiconductor channel layer within the gate recess region; and
depositing one or more layers of metallic material to fill the gate recess region;
wherein the one or more layers of metallic material comprises at least one of a work function metal layer and a gate electrode layer.

10. The method of claim 1 , wherein etching at least a portion of the REO layer exposed in the gate recess region to form a space between the semiconductor channel layer and the REO layer comprises isotropically etching an upper surface of the REO layer such that a resulting etched upper surface of the REO layer adjacent the semiconductor channel layer comprises a non-planar profile.

11. The method of claim 1 , wherein forming the nanosheet stack structure on the semiconductor substrate comprises:
epitaxially growing a first REO layer on the semiconductor substrate;
epitaxially growing a second REO layer on the first REO layer, wherein the second REO layer is formed of an REO material that has etch selectivity with respect to an REO material that forms the first REO layer;
epitaxially growing the semiconductor channel layer on the second REO layer; and
patterning the second REO layer and the semiconductor channel layer to form the nanosheet stack structure.

12. The method of claim 11 , wherein patterning the second REO layer and the semiconductor channel layer to form the nanosheet stack structure comprises etching the second REO layer selective to the first REO layer so that the first REO layer remains covering the semiconductor substrate.

13. The method of claim 12 , wherein the first source/drain region and the second source/drain region are formed in contact with portions of the REO layer which extend past opposing sides of the gate insulating spacer.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Wang Geng
• Zhang Qintao

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/3462

  Nanowires · CPC title