Semiconductor memory device with selection patterns, storage patterns, and a gap fill layer and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11856794-B2
Application number	US-202117364378-A
Country	US
Kind code	B2
Filing date	Jun 30, 2021
Priority date	Aug 24, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first memory cell provided on a substrate;
a second memory cell provided on the substrate and spaced apart from the first memory cell;
a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell; and
a gap fill layer covering the passivation layer,
wherein each of the first memory cell and the second memory cell comprises:
a selection pattern having ovonic threshold switching characteristics; and
a storage pattern provided on the selection pattern, wherein the passivation layer comprises:
a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell; and
an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell,

wherein the gap fill layer is not interposed between the selection pattern of the first memory cell and the selection pattern of the second memory cell,
wherein the gap fill layer is interposed between the storage pattern of the first memory cell and the storage pattern of the second memory cell, and
wherein the gap fill layer comprises a material having a lower thermal conductivity than the passivation layer.

2. The semiconductor memory device of claim 1 , wherein the lower portion of the passivation layer comprises a seam extending in a direction crossing a top surface of the substrate and interposed between the first memory cell and the second memory cell.

3. The semiconductor memory device of claim 2 , wherein a first thickness of the upper portion of the passivation layer from the side surface of the storage pattern of one among the first memory cell and the second memory cell to the gap fill layer is less than a second thickness of the lower portion of the passivation layer from a side surface of the selection pattern to the seam.

4. The semiconductor memory device of claim 1 , wherein a first width of the storage pattern of one among the first memory cell and the second memory cell is less than a second width of the selection pattern of the one among the first memory cell and the second memory cell.

5. The semiconductor memory device of claim 4 , wherein the passivation layer conformally extends along the side surface of the first memory cell and the side surface of the second memory cell.

6. The semiconductor memory device of claim 1 , wherein each of a width of the first memory cell and a width of the second memory cell decreases from a top surface of the substrate to a top surface of a respective one among the first memory cell and the second memory cell.

7. The semiconductor memory device of claim 6 , wherein the passivation layer conformally extends along the side surface of the first memory cell and the side surface of the second memory cell.

8. The semiconductor memory device of claim 1 , further comprising a third memory cell provided on the substrate and spaced apart from the first memory cell and the second memory cell,
wherein the third memory cell comprises the selection pattern and the storage pattern,
wherein the first memory cell and the second memory cell are provided along a first direction,
wherein the first memory cell and the third memory cell are provided along a second direction crossing the first direction, and
wherein the gap fill layer is interposed between the selection pattern of the second memory cell and the selection pattern of the third memory cell.

9. The semiconductor memory device of claim 1 , wherein each of the first memory cell and the second memory cell further comprises:
a lower electrode pattern interposed between the substrate and the selection pattern;
a middle electrode pattern interposed between the selection pattern and the storage pattern; and
an upper electrode pattern provided on the storage pattern.

10. The semiconductor memory device of claim 1 , wherein the selection pattern comprises a chalcogenide material, and
wherein the storage pattern comprises GeSbTe (GST).

11. The semiconductor memory device of claim 1 , wherein the passivation layer comprises any one or any combination of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride.

12. A semiconductor memory device comprising:
a substrate;
a plurality of first conductive lines provided on the substrate, each of the plurality of first conductive lines extending in a first direction;
a plurality of second conductive lines provided on the substrate, each of the plurality of second conductive lines extending in a second direction crossing the first direction;
a plurality of memory cells respectively disposed at intersections of the plurality of first conductive lines and the plurality of second conductive lines;
a passivation layer extending along a side surface of each of the plurality of memory cells; and
a gap fill layer covering the passivation layer,
wherein each of the plurality of memory cells comprises a lower electrode pattern, a selection pattern, a middle electrode pattern, a storage pattern, and an upper electrode pattern that are sequentially stacked on the substrate,
wherein a first thickness of the passivation layer surrounding the storage pattern is less than a second thickness of the passivation layer surrounding the selection pattern, and
wherein the gap fill layer comprises a material having a lower thermal conductivity than the passivation layer.

13. The semiconductor memory device of claim 12 , wherein the plurality of memory cells comprises a first memory cell and a second memory cell adjacent to the first memory cell, and
wherein the gap fill layer is not interposed between the selection pattern of the first memory cell and the selection pattern of the second memory cell.

14. The semiconductor memory device of claim 12 , wherein each of the lower electrode pattern, the middle electrode pattern, and the upper electrode pattern comprises a carbon (C) layer.

15. The semiconductor memory device of claim 14 , wherein each of the plurality of memory cells further comprises:
a first barrier pattern interposed between the middle electrode pattern and the storage pattern; and
a second barrier pattern interposed between the storage pattern and the upper electrode pattern.

16. The semiconductor memory device of claim 15 , wherein each of the first barrier pattern and the second barrier pattern comprises tungsten (W).

17. The semiconductor memory device of claim 12 , wherein each of the plurality of memory cells comprises:
a first side surface extending in the second direction; and
a second side surface extending in the first direction, and
wherein the passivation layer comprises:
a first layer extending in the first direction and covering the second side surface; and
a second layer extending in the second direction and covering the first side surface and a side surface of the first layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Dong Sung
• Kim Jong Uk
• Park Kwang Min
• Wu Zhe
• Lee Ja Bin
• Jung Jae Ho

Classifications

• H10B63/24 Primary

  of the Ovonic threshold switching type · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10B63/84 Primary

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title