Memory device and electronic apparatus including the same

Patent metadata

Field	Value
Publication number	US-9716129-B1
Application number	US-201615285922-A
Country	US
Kind code	B1
Filing date	Oct 5, 2016
Priority date	Jan 27, 2016
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.

First claim

What is claimed is:

1. A memory device, comprising:
a first electrode line layer provided on a substrate, the first electrode line layer comprising a plurality of first electrode lines which extend in a first direction and are spaced apart from each other;
a second electrode line layer provided on the first electrode line layer, the second electrode line layer comprising a plurality of second electrode lines which extend in a second direction different from the first direction and are spaced apart from each other;
a third electrode line layer provided on the second electrode line layer, the third electrode line layer comprising a plurality of first electrode lines;
a first memory cell layer provided between the first and second electrode line layers, the first memory cell layer comprising a plurality of first memory cells arranged at respective intersections of the plurality of first electrode lines of the first electrode line layer and the plurality of second electrode lines;
a second memory cell layer provided between the second and third electrode line layers, the second memory cell layer comprising a plurality of second memory cells arranged at respective intersections of the plurality of second electrode lines and the plurality of first electrode lines of the third electrode line layer;
a first spacer covering side surfaces of each of the plurality of first memory cells; and
a second spacer covering side surfaces of each of the plurality of second memory cells,
wherein each of the plurality of first and second memory cells comprises a selection device, an electrode, and a variable resistance pattern stacked in an upward or downward direction, and
the first spacer has a thickness different from that of the second spacer.

2. The memory device of claim 1 , wherein the thickness of each of the first and second spacers is a thickness measured in a direction normal to a side surface of the variable resistance pattern, and
the thickness of the first or second spacer is adjusted so that the first and second memory cells have substantially the same resistance.

3. The memory device of claim 2 , wherein the resistance is a set or reset resistance of the first and second memory cells.

4. The memory device of claim 3 , wherein the set resistance of the first or second memory cells covered by the first or second spacer having a large thickness is substantially the same as the set resistance of the second memory cells or the first memory cells covered by the second spacer or the first spacer having a small thickness.

5. The memory device of claim 1 , wherein each of the first and second memory cells comprises a heating electrode in contact with the variable resistance pattern.

6. The memory device of claim 1 , wherein each of the first and second memory cells comprises a lower electrode in contact with the selection device, and
side surfaces of the selection device and the lower electrode are covered by an inner spacer.

7. The memory device of claim 1 , wherein one of the first and second spacers comprises a material exerting a compressive stress on the variable resistance pattern, and
the other of the first and second spacers comprises a material exerting a tensile stress on the variable resistance pattern.

8. The memory device of claim 1 , further comprising:
at least one first upper electrode line layer provided on the third electrode line layer, each of the at least one first upper electrode line layer comprising a plurality of first electrode lines;
at least one second upper electrode line layer provided on a corresponding one of the at least one first upper electrode line layer, each of the at least one second upper electrode line layer comprising a plurality of second electrode lines; and
at least two upper memory cell layers provided between the first upper electrode line layer and the second upper electrode line layer, each of the at least two upper memory cell layers comprising a plurality of memory cells arranged at respective intersections of the plurality of first electrode lines of the first upper electrode line layer and the plurality of second electrode lines of the second upper electrode line layer.

9. The memory device of claim 1 , wherein the variable resistance pattern comprises at least one of GeSbTe, InSbTe, and BiSbTe, or comprises a super lattice structure, in which GeTe and SbTe layers are alternately stacked.

10. The memory device of claim 1 , wherein each of the first and second memory cells comprises a heating electrode in contact with the variable resistance pattern, and
the heating electrode comprises a carbon-based conductive material.

11. The memory device of claim 1 , wherein the selection device comprises one of an ovonic threshold switching (OTS) device, a diode, and a transistor.

12. The memory device of claim 1 , wherein at least one of the selection device and the variable resistance pattern has one of a pillar structure, a pyramid structure, an “L”-shaped structure, and a dash-shaped structure.

13. A memory device, comprising:
a first electrode line layer provided on a substrate, the first electrode line layer comprising a plurality of first electrode lines which extend in a first direction and are spaced apart from each other;
a second electrode line layer provided on the first electrode line layer, the second electrode line layer comprising a plurality of second electrode lines which extend in a second direction different from the first direction and are spaced apart from each other;
a third electrode line layer provided on the second electrode line layer, the third electrode line layer comprising a plurality of first electrode lines;
a first memory cell layer provided between the first and second electrode line layers, the first memory cell layer comprising a plurality of first memory cells arranged at respective intersections of the plurality of first electrode lines of the first electrode line layer and the plurality of second electrode lines;
a second memory cell layer provided between the second and third electrode line layers, the second memory cell layer comprising a plurality of second memory cells arranged at respective intersections of the plurality of second electrode lines and the plurality of first electrode lines of the third electrode line layer;
a first spacer covering side surfaces of each of the plurality of first memory cells; and
a second spacer covering side surfaces of each of the plurality of second memory cells,
wherein each of the plurality of first and second memory cells comprises a selection device, an electrode, and a variable resistance pattern stacked in an upward or downward direction, and
at least one of the first spacer and the second spacer comprises a material exerting a compressive or tensile stress on the variable resistance pattern.

14. The memory device of claim 13 , wherein one of the first spacer and the second spacer comprises a material exerting a compressive stress on the variable resistance pattern, and the other comprises a material exerting a tensile stress on the variable resistance pattern.

15. The memory device of claim 13 , wherein each of the first and second memory cells comprises a lower electrode in contact with the selection device,
side surfaces of the selection device and the lower electrode are covered by an inner spacer, and
at least one of the first spacer and the second spacer covers the inner spacer.

16. The memory device of claim 13 , further comprising:
at least one first upper electrode line layer provided on the third electrode line layer, each of the at least one fir

Assignees

• Samsung Electronics Co Ltd

Inventors

• Sim Kyu-Rie
• Koh Gwan-Hyeob
• Kang Dae-Hwan

Classifications

• H01L45/06

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L27/2427

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/126

  Electricity · mapped topic