Damascene process for forming three-dimensional cross rail phase change memory devices

Patent metadata

Field	Value
Publication number	US-10468596-B2
Application number	US-201815901633-A
Country	US
Kind code	B2
Filing date	Feb 21, 2018
Priority date	Feb 21, 2018
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

First stacked rail structures including a first conductive rail, a selector rail, and a sacrificial material rail and separated by first trenches are formed over a substrate. First dielectric isolation structures are formed in the first trenches. Second trenches are formed, which divides the first stacked rail structures above the first conductive rails. Second dielectric isolation structures in the second trenches. Pillar structures are formed, which include a respective vertical stack of a selector element and a sacrificial material pillar. The sacrificial material pillars are replaced with phase change memory material pillars by a damascene method that deposits and planarizes a phase change memory material. Second conductive rails are formed over the phase change memory material pillars. Sidewalls of the phase change memory material pillars are not subjected to etch damage, thereby enhancing electrical characteristics of the phase change memory material pillars.

First claim

What is claimed is:

1. A method of manufacturing a phase change memory device, comprising:
forming first stacked rail structures laterally extending along a first horizontal direction and laterally spaced apart by first trenches along a second horizontal direction over a substrate, wherein each of the first stacked rail structures comprises a first conductive rail, a first selector rail, and a first sacrificial material rail;
forming first dielectric isolation structures in the first trenches;
forming second trenches laterally extending along the second horizontal through the first sacrificial material rails, the first selector rails, and the first dielectric isolation structures;
forming second dielectric isolation structures in the second trenches, wherein remaining portions of the first sacrificial material rails and first selector rails constitute in-process pillar structures including a respective vertical stack of a first selector element and a first sacrificial material pillar;
forming first cavities by removing the first sacrificial material pillars without removing the first and second dielectric isolation structures and the first selector elements;
forming first phase change memory material pillars in the first cavities by a damascene method that deposits a first phase change memory material in the first cavities and removes portions of the first phase change memory material from outside the first cavities;
vertically recessing the first phase change memory material pillars in upper regions of the first cavities to form recess volumes that are not filled with any solid material;
forming a stack of an upper conductive liner plate and a barrier material portion in each of the recess volumes by depositing a metal in the recess volumes, removing portions of the metal from outside the recess volumes by a first planarization process, and removing the metal from upper regions of the recess volumes, wherein remaining portions of the metal in lower regions of the recess volumes constitute the upper conductive liner plates; and depositing a barrier material in the upper portions of the recess volumes, and removing portions of the barrier material from outside the recess volumes by a second planarization process, wherein remaining volumes of the barrier material constitute the barrier material portions; and
forming second conductive rails laterally extending along the second horizontal direction over the first phase change memory material pillars.

2. The method of claim 1 , wherein:
the first selector element comprises a chalcogenide ovonic threshold switch material; and
the first phase change memory material is selected from germanium antimony telluride compounds, germanium antimony compounds, indium germanium telluride compounds, aluminum selenium telluride compounds, indium selenium telluride compounds, and aluminum indium selenium telluride compounds.

3. A method of manufacturing a phase change memory device, comprising:
forming first stacked rail structures laterally extending along a first horizontal direction and laterally spaced apart by first trenches along a second horizontal direction over a substrate, wherein each of the first stacked rail structures comprises a first conductive rail, a first selector rail, and a first sacrificial material rail;
forming first dielectric isolation structures in the first trenches;
forming second trenches laterally extending along the second horizontal through the first sacrificial material rails, the first selector rails, and the first dielectric isolation structures;
forming second dielectric isolation structures in the second trenches, wherein remaining portions of the first sacrificial material rails and first selector rails constitute in-process pillar structures including a respective vertical stack of a first selector element and a first sacrificial material pillar;
forming first cavities by removing the first sacrificial material pillars without removing the first and second dielectric isolation structures and the first selector elements;
forming first phase change memory material pillars in the first cavities by a damascene method that deposits a first phase change memory material in the first cavities and removes portions of the first phase change memory material from outside the first cavities;
depositing a layer stack including an upper conductive liner layer and a barrier material layer over the first and second dielectric isolation structures and the first phase change memory material pillars;
patterning the layer stack into a two-dimensional array of stacks of an upper conductive liner plate and a barrier material portion that overlie a respective one of the first phase change memory material pillars;
forming an insulating matrix layer by filling gaps among the two-dimensional array of the stacks with a dielectric material and planarizing the dielectric material to provide a top surface that is coplanar with top surfaces of the barrier material portions; and
forming second conductive rails laterally extending along the second horizontal direction over the first phase change memory material pillars, wherein the second conductive rails are formed on a respective row of the stacks within the two-dimensional array of the stacks that laterally extends along the second horizontal direction.

4. The method of claim 3 , wherein:
the second conductive rails are formed on top surfaces of the barrier material portions and on a top surface of the insulating matrix layer; and
the top surfaces of the barrier material portions are vertically offset from a horizontal plane including the top surfaces of the first dielectric isolation structures and top surfaces of the second dielectric isolation structures by a thickness of the insulating matrix layer.

5. The method of claim 3 , wherein:
the first selector element comprises a chalcogenide ovonic threshold switch material; and
the first phase change memory material is selected from germanium antimony telluride compounds, germanium antimony compounds, indium germanium telluride compounds, aluminum selenium telluride compounds, indium selenium telluride compounds, and aluminum indium selenium telluride compounds.

Assignees

• Sandisk Technologies Llc

Inventors

• Makala Raghuveer S
• Kanakamedala Senaka
• Lee Yao-Sheng

Classifications

• H01L45/124

  Electricity · mapped topic

• H01L27/2427

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L45/065

  Electricity · mapped topic

• H01L45/1683 Primary

  Electricity · mapped topic