Method of forming a sensor device

Patent metadata

Field	Value
Publication number	US-11855019-B2
Application number	US-202117173237-A
Country	US
Kind code	B2
Filing date	Feb 11, 2021
Priority date	Feb 11, 2021
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. A plurality of electrodes and a bond pad are formed in a dielectric region. A passivation layer is formed on each electrode in the plurality of electrodes and the bond pad. A barrier layer is formed on the passivation layer. A plurality of trenches are formed to extend through the barrier layer and into the dielectric region. Formation of the trenches simultaneously exposes an upper surface of the bond pad. A moisture sensitive dielectric layer is formed on the barrier layer. Formation of the moisture sensitive dielectric layer also fills the trenches to form a plurality of projections, each projection being formed between two electrodes in the plurality of electrodes.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a plurality of electrodes and a bond pad in a dielectric region, wherein the plurality of electrodes is located in a first device region and the bond pad is located in a second device region;
forming a passivation layer on each electrode in the plurality of electrodes and the bond pad;
forming a barrier layer on the passivation layer;
forming a plurality of trenches that extend through the barrier layer and into the dielectric region, the forming of the trenches simultaneously exposing an upper surface of the bond pad; and
forming a moisture sensitive dielectric layer on the barrier layer, wherein the forming of the moisture sensitive dielectric layer also fills the trenches to form a plurality of projections, each projection being formed between two electrodes in the plurality of electrodes.

2. The method of claim 1 , further comprising:
forming a plurality of recesses by patterning the passivation layer on the electrodes, wherein each recess is formed in the dielectric region and between two electrodes in the plurality of electrodes;
forming the barrier layer to fill the recesses.

3. The method of claim 2 , wherein the forming of the trenches includes simultaneously etching the dielectric region and the barrier layer, and wherein the dielectric region has a material with the same etch selectivity as the barrier layer.

4. The method of claim 3 , wherein the upper surface of the bond pad is exposed by etching the passivation layer and the barrier layer.

5. The method of claim 4 , further comprising etching the moisture sensitive dielectric layer to expose the upper surface of the bond pad.

6. The method of claim 3 , wherein the forming of the trenches includes etching the dielectric region until bottom surfaces of the trenches contact an etch stop layer formed below the dielectric region.

7. The method of claim 6 , wherein the trenches are formed within the first device region.

8. The method of claim 1 , wherein the electrodes are formed to have an upper surface that is substantially coplanar with the upper surface of the bond pad.

9. The method of claim 8 , wherein the electrodes and the bond pad are formed in the dielectric region using a dual damascene process.

10. The method of claim 1 , wherein the moisture sensitive dielectric layer extends over each electrode in the plurality of electrodes.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• KHOR Ee Jan
• Tan Juan Boon
• Chockalingam Ramasamy

Classifications

• H10W72/981

  Auxiliary members, e.g. spacers · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title