Semiconductor device with airgap spacer formation from backside of wafer

Patent metadata

Field	Value
Publication number	US-11848384-B2
Application number	US-202117485580-A
Country	US
Kind code	B2
Filing date	Sep 27, 2021
Priority date	Sep 27, 2021
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A semiconductor structure includes a substrate and a field effect transistor disposed on the substrate. The field effect transistor includes a vertical fin, source and drain regions separated by a gate region, a gate structure disposed over the gate region and a gate airgap spacer at least partially disposed about the gate structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a field effect transistor disposed on a substrate, the field effect transistor including:
a vertical fin extending from the substrate;
source and drain regions separated by a gate region;
a gate structure disposed over the gate region; and
a gate airgap spacer at least partially disposed about the gate structure; and

a back end of the line device disposed over the gate structure.

2. The semiconductor structure according to claim 1 including a plurality of gate structures, each gate structure having a gate airgap spacer at least partially disposed therearound.

3. The semiconductor structure according to claim 1 wherein the vertical fin is at least partially surrounded by a fin airgap spacer.

4. The semiconductor structure according to claim 3 wherein the fin airgap spacer extends to the substrate.

5. The semiconductor structure according to claim 1 wherein the back end of the line device is coupled to the field effect transistor.

6. The semiconductor structure according to claim 5 including a substrate wafer coupled to the back end of the line device.

7. The semiconductor structure according to claim 6 including a backside power rail and a backside power distribution network coupled to the substrate wafer remote from the back end of the line device.

8. The semiconductor structure according to claim 7 wherein the field effect transistor includes a contact via in electrical contact with one of the source and drain regions.

9. The semiconductor structure according to claim 8 including one or more backside via contacts in communication with the backside power rail.

10. The semiconductor structure according to claim 1 wherein the vertical fin includes a vertical dielectric fin portion and a vertical semiconductor fin portion over the vertical dielectric fin portion.

11. A semiconductor device, comprising:
a first device formed on a first side of a substrate, the first device including source and drain regions separated by a gate region, a fin and a gate structure disposed over the gate region;
an airgap spacer extending to a second side of the substrate;
a second device formed on the second side of the substrate and coupled to the first device; and
a back end of the line device coupled to the first device and remote from the second device.

12. The semiconductor device according to claim 11 including a gate airgap spacer at least partially disposed about the gate structure.

13. The semiconductor device according to claim 12 wherein the fin is a vertical fin and further including a fin airgap spacer at least partially disposed about the vertical fin.

14. The semiconductor device according to claim 13 wherein the fin airgap spacer extends to the second side of the substrate.

15. The semiconductor device according to claim 14 wherein the vertical fin includes a vertical dielectric fin portion and a vertical semiconductor fin portion over the vertical dielectric fin portion.

16. The semiconductor device according to claim 11 wherein the second device includes a backside power rail and via contacts connecting the backside power rail to the first device.

17. An integrated circuit, comprising:
a plurality of semiconductor structures, wherein at least one of the plurality of semiconductor structures comprises:
a field effect transistor disposed on a substrate, the field effect transistor comprising:
a vertical fin extending from the substrate;
source and drain regions separated by a gate region;
a gate structure disposed over the gate region; and
a gate airgap spacer at least partially disposed about the gate structure; and

a back end of the line device disposed over the gate structure.

18. The integrated circuit according to claim 17 comprising a plurality of gate structures, each gate structure having a gate airgap spacer at least partially disposed therearound.

19. The integrated circuit according to claim 17 wherein the back end of the line device is coupled to the field effect transistor.

20. The integrated circuit according to claim 19 comprising a substrate wafer coupled to the back end of the line device, and a backside power rail and a backside power distribution network coupled to the substrate wafer remote from the back end of the line device.

Assignees

• IBM

Inventors

• Xie Ruilong
• Frougier Julien
• Cheng Kangguo
• Park Chanro

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/0698

  Local interconnections · CPC title