Semiconductor device integrating backside power grid and related integrated circuit and fabrication method

Patent metadata

Field	Value
Publication number	US-10700207-B2
Application number	US-201815993149-A
Country	US
Kind code	B2
Filing date	May 30, 2018
Priority date	Nov 30, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a dielectric region situated on the substrate;
a plurality of conductive regions situated on the dielectric region;
a first conductive rail situated within the dielectric region, the first conductive rail being electrically connected to a first conductive region of the plurality of conductive regions, wherein the first conductive region contacts a top surface of the first conductive rail at a level where the first conductive region contacts a top surface of the dielectric region; and
a conductive structure penetrating through the substrate and formed under the first conductive rail, the conductive structure being electrically connected to the first conductive rail.

2. The semiconductor device of claim 1 , the conductive structure comprises a conductive through-substrate via.

3. The semiconductor device of claim 1 , further comprising:
a power grid conductor situated under the substrate, the power grid conductor being electrically connected to the conductive structure.

4. The semiconductor device of claim 3 , further comprising:
a metal pad situated between the substrate and the power grid conductor, the metal pad configured to electrically connect the power grid conductor to the substrate.

5. The semiconductor device of claim 1 , further comprising:
a fin structure protruding from the substrate and the dielectric region and contacting the conductive structure.

6. The semiconductor device of claim 5 , further comprising:
a second conductive rail situated within the dielectric region and electrically connected to the conductive structure, wherein the first conductive rail faces a first sidewall of the fin structure, and the second conductive rail faces a second sidewall of the fin structure.

7. The semiconductor device of claim 5 , wherein the plurality of conductive regions comprises a source region, a gate region and a drain region, and the fin structure, the source region, the gate region and the drain region are configured to form a fin field-effect transistor.

8. The semiconductor device of claim 1 , further comprising:
a first metal wire electrically connected to a second conductive region of the plurality of conductive regions, the first metal wire extending in a first direction;
a second metal wire extending in a second direction different from the first direction; and
a conductive through via located on the first metal wire and below the second metal wire, the first metal wire being electrically connected to the second metal wire through the conductive through via.

9. The semiconductor device of claim 8 , wherein the second conductive region is electrically connected to the first conductive region through the first conductive rail, or is isolated from the first conductive rail by the dielectric region.

10. An integrated circuit, comprising:
a substrate;
a dielectric region situated on the substrate;
a first fin field-effect transistor, comprising a first source region, a first gate region and a first drain region situated on the dielectric region;
a conductive rail situated within the dielectric region, the conductive rail being electrically connected to a first terminal region selected from among the first source region, the first gate region and the first drain region, wherein the first terminal region electrically connected to the conductive rail contacts each of respective portions of the dielectric region located on opposite sides of the conductive rail; and
a conductive structure penetrating through the substrate and formed under the conductive rail, the conductive structure being electrically connected to the conductive rail.

11. The integrated circuit of claim 10 , wherein the first fin field-effect transistor further comprises a fin structure protruding from the substrate and the dielectric region and contacting the conductive structure.

12. The integrated circuit of claim 10 , the conductive structure comprises a conductive through-substrate via.

13. The integrated circuit of claim 10 , further comprising:
a power grid conductor situated under the substrate, the power grid conductor being electrically connected to the conductive structure.

14. The integrated circuit of claim 13 , further comprising:
a metal pad situated between the substrate and the power grid conductor, the metal pad configured to electrically connect the power grid conductor to the substrate.

15. The integrated circuit of claim 10 , further comprising:
a second fin field-effect transistor, comprising a second source region, a second gate region and a second drain region situated on the dielectric region; and
a first metal wire electrically connected to a second conductive region selected from among the first source region, the first gate region, the first drain region, the second source region, the second gate region and the second drain region, the first metal wire extending in a first direction;
a second metal wire extending in a second direction different from the first direction; and
a conductive through via located on the first metal wire and below the second metal wire, the first metal wire being electrically connected to the second metal wire through the conductive through via.

16. A semiconductor device, comprising:
a substrate;
a dielectric region situated on the substrate;
a fin structure protruding from the substrate and the dielectric region;
a conductive rail situated within the dielectric region, the conductive rail facing a sidewall of the fin structure, wherein a bottom surface of the conductive rail is at a level equal to or higher than a bottom surface of a fin of the fin structure; and
a conductive structure penetrating through the substrate and formed under the conductive rail, the conductive structure being electrically connected to the conductive rail.

17. The semiconductor device of claim 16 , further comprising:
a power grid conductor situated under the substrate, the power grid conductor being electrically connected to the conductive rail through the conductive structure.

18. The semiconductor device of claim 16 , further comprising:
a conductive region situated on the dielectric region and electrically connected to the conductive rail.

19. The semiconductor device of claim 16 , further comprising:
a conductive region situated on the dielectric region, the conductive region being isolated from the conductive rail by the dielectric region.

20. The semiconductor device of claim 16 , wherein the conductive structure is further formed under the fin structure, and electrically connected to the fin structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih-Liang
• Chou Lei-Chun
• Liu Jack
• Sio Kam-Tou
• Yang Hui-Ting
• Lin Wei-Cheng
• Liou Chun-Hung
• Tzeng Jiann-Tyng
• Young Chew-Yuen

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/042

  the barrier, adhesion or liner layers being seed or nucleation layers · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title