Three-dimensional memory device containing air gap rails and method of making thereof

Patent metadata

Field	Value
Publication number	US-10290648-B1
Application number	US-201715834261-A
Country	US
Kind code	B1
Filing date	Dec 7, 2017
Priority date	Dec 7, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

An alternating stack of insulating layers and spacer material layers located over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures are formed through the alternating stack. After formation of a backside trench, electrically-conductive-layer-level recessed cavities are formed by laterally recessing the electrically conductive layers around the backside trench. Electrically conductive rails are formed on remaining portions of the electrically conductive layers by selective deposition of a conductive material. Insulating-layer-level recessed cavities are formed by laterally recessing the insulating layers around the backside trench. A continuous insulating material layer can be formed in the insulating-layer-level recessed cavities with air gap rails cavities to reduce capacitive coupling among the electrically conducive rails.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises respective charge storage elements and a vertical semiconductor channel laterally surrounded by the respective charge storage elements;
electrically conductive rails contacting a sidewall of a respective one of the electrically conductive layers and laterally extending along a horizontal direction; and
a continuous insulating material layer including a vertical portion extending vertically from a bottommost one of the electrically conductive rails to a topmost one of the electrically conductive rails and laterally protruding portions that laterally protrude between each vertically neighboring pair of the electrically conductive rails, wherein the laterally protruding portions include air gap rails.

2. The three-dimensional memory device of claim 1 , wherein:
the continuous insulating material layer is located in a backside trench; and
each air gap rail includes a laterally extending cavity having a first height more proximal to the backside trench and a second height greater than the first height more distal from the backside trench.

3. The three-dimensional memory device of claim 2 , wherein the continuous insulating material layer completely fills the backside trench.

4. The three-dimensional memory device of claim 1 , wherein:
vertical interfaces between the laterally protruding portions of the continuous insulating material layer and the insulating layers are within a same vertical plane; and
the vertical portion of the continuous insulating material layer has a variable lateral width that increases with a distance from the substrate.

5. The three-dimensional memory device of claim 1 , further comprising backside blocking dielectric layers that are located between each vertically neighboring pair of an insulating layer and an electrically conductive layer.

6. The three-dimensional memory device of claim 5 , wherein each of the electrically conductive rails contacts a respective one of the backside blocking dielectric layers, has a top surface within a horizontal plane including a topmost surface of the respective one of the backside blocking dielectric layers, and a bottom surface that is within a horizontal plane including a bottommost surface of the respective one of the backside blocking dielectric layer.

7. The three-dimensional memory device of claim 5 , wherein, for each of the electrically conductive rails, a height of an interface between an electrically conductive rail and a respective one of the electrically conductive layers is less than a vertical thickness of the electrically conductive rail by twice a thickness of the backside blocking dielectric layers.

8. The three-dimensional memory device of claim 5 , wherein the laterally protruding portions of the continuous insulating material layer contact horizontal surfaces of the backside blocking dielectric layers.

9. The three-dimensional memory device of claim 1 , wherein the electrically conductive rails have a different material composition than the electrically conductive layers.

10. The three-dimensional memory device of claim 1 , wherein the continuous insulating material layer includes a vertically-extending cavity that vertically extends through at least one half of all electrically conductive layers within the alternating stack and is laterally spaced from each of the air gap rails.

11. The three-dimensional memory device of claim 1 , further comprising:
a source region located within the substrate; and
a source contact via structure that is laterally surrounded by the vertical portion of the continuous insulating material layer.

12. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

Assignees

• Sandisk Technologies Llc

Inventors

• Zhou Fei
• Makala Raghuveer S
• Sharangpani Rahul
• RAJASHEKHAR Adarsh

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title