Air gap isolation in non-volatile memory

Patent metadata

Field	Value
Publication number	US-9460958-B2
Application number	US-201314091101-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Jun 19, 2010
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.

First claim

What is claimed is:

1. A method of fabricating non-volatile storage, comprising:
forming a first layer stack column and a second layer stack column elongated in a column direction over a substrate, each layer stack column having two vertical sidewalls and including a charge storage strip over a tunnel dielectric strip, the first layer stack column overlying a first active area of the substrate and the second layer stack column overlying a second active area of the substrate;
etching the substrate to define an isolation region between the first active area and the second active area;
selectively growing a cap on the charge storage strip of the first layer stack column and the charge storage strip of the second layer stack column, the cap extending vertically along at least a portion of a first vertical sidewall of the charge storage strip of the first column and a first vertical sidewall of the charge storage strip of the second column; and
forming a bit line air gap in the isolation region having an upper endpoint defined at least partially by the cap;
wherein etching the substrate is performed prior to forming the first layer stack column and the second layer stack column.

2. A method according to claim 1 , wherein:
the isolation region is a first isolation region;
the method further comprises forming a second isolation region and a third isolation region in the substrate, the second isolation region being adjacent to the first active area and a fourth active area and the third isolation region being adjacent to the second active area and a fifth active area.

3. A method according to claim 2 , further comprising:
forming an isolation material in each isolation region, the isolation material including a first protrusion extending above the substrate surface from the first isolation region, a second protrusion extending above the substrate surface from the second isolation region and a third protrusion extending above the substrate surface from the third isolation region;
slimming a dimension of each protrusion in the row direction;
forming the charge storage strip for the first column by depositing charge storage material between the first protrusion and the second protrusion after slimming the dimension of each protrusion in the row direction; and
forming the charge storage strip for the second column by depositing charge storage material between the first protrusion and the third protrusion after slimming the dimension of each protrusion in the row direction.

4. A method according to claim 3 , wherein:
the charge storage strip for the first column has a first vertical sidewall that overlies the second isolation region and a second vertical sidewall that overlies the first isolation region;
the charge storage strip for the second column has a first vertical sidewall that overlies the first isolation region and a second vertical sidewall that overlies the third isolation region.

5. A method according to claim 4 , further comprising:
removing the protrusions and recessing the isolation material below a level of the substrate surface after forming each charge storage strip.

6. A method according to claim 5 , wherein:
selectively growing the cap between the first layer stack column and the second layer stack column includes thermally oxidizing at least a portion of the second vertical sidewall of the charge storage strip for the first column and the first vertical sidewall of the charge storage strip for the second column to grow the cap between the first and second charge storage strips; and
the cap includes oxide that grows from the second vertical sidewall of the charge storage strip for the first column and oxide that grows that grows from the first vertical sidewall of the charge storage strip for the second column, the oxides meeting above the first isolation region and at least partially overlying air to from the bit line air gap in the first isolation region.

7. A method according to claim 2 , further comprising:
forming an intermediate dielectric layer over an upper surface and along vertical sidewalls of the charge storage strip of the first layer stack column and over an upper surface and along vertical sidewalls of the charge storage strip of the second layer stack column; and
forming a control gate layer over the intermediate dielectric layer, the control gate layer extending below the upper surface of the charge storage strips between adjacent portions of the intermediate dielectric layer.

8. A method according to claim 7 , further comprising:
etching the control gate layer into a plurality of control gates;
etching the charge storage strip for the first column into a first plurality of charge storage regions; and
etching the charge storage strip for the second column into a second plurality of charge storage regions;
wherein the plurality of control gates includes a first control gate separated from a first charge storage region of the first plurality and a first charge storage region of the second plurality;
wherein the plurality of control gates includes a second control gate separated from a second charge storage region of the first plurality and a second charge storage region of the second plurality.

9. A method according to claim 8 , wherein:
etching the control gate layer, the charge storage strip for the first column and the charge storage strip for the second column forms a plurality of layer stack rows including a first layer stack row and a second layer stack row;
the first layer stack row includes the first control gate, a first intermediate dielectric strip, and the first plurality of charge storage regions;
the second layer stack row includes the second control gate, a second intermediate dielectric strip, and the second plurality of charge storage regions; and
forming a plurality of word line air gaps including a first word line air gap formed between the first layer stack row and the second layer stack row.

10. A method according to claim 9 , wherein:
the first word line air gap extends vertically, with respect to the substrate surface, from a level above the substrate surface to at least a level of an upper surface of the first and second control gate.

11. A method of fabricating non-volatile storage, comprising:
etching a substrate to define a plurality of isolation regions;
forming an isolation material in each isolation region, the isolation material including a plurality of protrusions extending above the substrate surface from each isolation region;
after etching the substrate and forming the isolation material, forming a plurality of layer stack columns elongated in a column direction over the substrate, each layer stack column including a charge storage strip extending in a row direction between adjacent protrusions of the isolation material and a tunnel dielectric strip underlying the charge storage strip;
removing at least a portion of the isolation material from the plurality of isolation regions including the plurality of protrusions to form a plurality of voids including air below the substrate surface; and
selectively growing a plurality of caps in contact with the plurality of voids after removing the isolation material from the plurality of isolation regions, each cap elongated in the column direction and extending in the row direction between adjacent layer stack columns, each cap defining an upper endpoint of a bit line air gap in an underlying isolation region.

12. The method of claim 11 , further comprising:
slimming a dimension of each protrusion in the row direction prior to forming the plurality of layer stack columns; and
forming each charge storage strip for the layer stack colum

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Purayath Vinod R
• Kinoshita Hiroyuki
• Pham Tuan

Classifications

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20 Primary

  Air gaps · CPC title

• H01L27/11568

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic