Semiconductor memory device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-11844211-B2
Application number	US-202117340148-A
Country	US
Kind code	B2
Filing date	Jun 7, 2021
Priority date	Oct 15, 2020
Publication date	Dec 12, 2023
Grant date	Dec 12, 2023

Abstract

A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first semiconductor chip including an upper input/output pad;
a second semiconductor chip including a lower input/output pad; and
a substrate attachment film which attaches the first semiconductor chip and the second semiconductor chip,
wherein each of the first semiconductor chip and the second semiconductor chip further includes:
a first substrate which includes a first side facing the substrate attachment film and a second side opposite to the first side,
a mold structure including a plurality of gate electrodes stacked sequentially on the first side of the first substrate,
a channel structure which penetrates the mold structure and intersects the plurality of gate electrodes,
a second substrate which includes a third side facing the first side and a fourth side opposite to the third side,
a first circuit element on the third side of the second substrate, and
a contact via which penetrates the first substrate and is connected to the first circuit element,

wherein the substrate attachment film attaches the second substrate of the first semiconductor chip and the second substrate of the second semiconductor chip,
wherein the upper input/output pad is placed on the second side of the first semiconductor chip and contacts the contact via of the first semiconductor chip, and
wherein the lower input/output pad is placed on the second side of the second semiconductor chip and contacts the contact via of the second semiconductor chip.

2. The semiconductor memory device of claim 1 , wherein each of the first semiconductor chip and the second semiconductor chip further includes:
an interlayer insulating film which covers the mold structure on the first side of the first substrate, and
a through via which penetrates the interlayer insulating film and connects the first circuit element and the contact via.

3. The semiconductor memory device of claim 2 , wherein each of the first semiconductor chip and the second semiconductor chip further includes:
a first inter-wiring insulating film which covers the interlayer insulating film, and
a second inter-wiring insulating film which is attached to the first inter-wiring insulating film and covers the first circuit element.

4. The semiconductor memory device of claim 1 , wherein each of the first semiconductor chip and the second semiconductor chip further includes:
a block isolation region which extends in a first direction and cuts the mold structure, and
a bit line which extends in a second direction intersecting the first direction between the mold structure and the second substrate and is connected to the channel structure.

5. The semiconductor memory device of claim 1 , wherein the channel structure includes a semiconductor pattern intersecting the plurality of gate electrodes, and an information storage film interposed between the semiconductor pattern and the mold structure.

6. The semiconductor memory device of claim 1 , wherein the substrate attachment film includes a first attachment film which covers the fourth side of the first semiconductor chip, and a second attachment film which is attached to the first attachment film and covers the fourth side of the second semiconductor chip.

7. The semiconductor memory device of claim 6 , wherein the substrate attachment film further includes a first attachment pad in the first attachment film, and a second attachment pad attached to the first attachment pad in the second attachment film.

8. A semiconductor memory device comprising:
a first semiconductor chip including an upper input/output pad; and
a second semiconductor chip including a lower input/output pad and attached to the first semiconductor chip,
wherein each of the first semiconductor chip and the second semiconductor chip further includes:
a first substrate including a first side and a second side opposite to each other,
a mold structure including a plurality of gate electrodes stacked sequentially on the first side of the first substrate, and
a channel structure which penetrates the mold structure and intersects the plurality of gate electrodes,
a second substrate including a third side facing the first side and a fourth side opposite to the third side, and
a contact via penetrating the first substrate,

wherein the fourth side of the first semiconductor chip faces the fourth side of the second semiconductor chip,
wherein the upper input/output pad is connected to the contact via of the first semiconductor chip, and
wherein the lower input/output pad is connected to the contact via of the second semiconductor chip.

9. The semiconductor memory device of claim 8 ,
wherein each of the first semiconductor chip and the second semiconductor chip further includes a circuit element on the third side of the second substrate, and
wherein the contact via is connected to the circuit element.

10. The semiconductor memory device of claim 8 , wherein a width of the contact via decreases from the second side of the first substrate toward the first side of the first substrate.

11. The semiconductor memory device of claim 8 , wherein the contact via includes a conductive pattern, and a spacer film extending along a side face of the conductive pattern to separate the conductive pattern from the first substrate.

12. The semiconductor memory device of claim 8 , wherein each of the first semiconductor chip and the second semiconductor chip further includes:
an interlayer insulating film which covers the mold structure on the first side of the first substrate, and
a first through via which penetrates the interlayer insulating film and is connected to the contact via.

13. The semiconductor memory device of claim 12 , wherein the first through via is spaced apart from the mold structure.

14. The semiconductor memory device of claim 12 , wherein each of the first semiconductor chip and the second semiconductor chip further includes a second through via which penetrates the interlayer insulating film and is connected to the first substrate.

15. The semiconductor memory device of claim 8 , wherein each of the first semiconductor chip and the second semiconductor chip further includes a through via which penetrates the mold structure and is connected to the contact via.

16. The semiconductor memory device of claim 8 , further comprising:
a third semiconductor chip which includes the first substrate, the mold structure, the channel structure, and the contact via, and is attached to the first semiconductor chip,
wherein the second side of the first semiconductor chip faces the first side of the third semiconductor chip.

17. The semiconductor memory device of claim 16 , further comprising:
a substrate attachment film which attaches the first semiconductor chip and the second semiconductor chip; and
a chip attachment film which attaches the first semiconductor chip and the third semiconductor chip,
wherein a thickness of the substrate attachment film is smaller than a thickness of the chip attachment film.

18. An electronic system comprising:
a main board;
a semiconductor memory device on the main board; and
a controller which is electrically connected to the semiconductor memory device on the main board,
wherein the semiconductor memory device includes a first semiconductor chip including an upper input/output pad, and a second semiconductor chip including a lower input/output pad and attached to the first semiconductor chip,
wherein each of the first semiconductor chip and the second semiconductor chip incl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Jae Ho
• Kim Ji Won
• Hwang Sung-Min
• Lim Joon-Sung
• Sung Suk Kang

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title