Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Patent metadata

Field	Value
Publication number	US-2020258816-A1
Application number	US-202016829591-A
Country	US
Kind code	A1
Filing date	Mar 25, 2020
Priority date	Feb 13, 2019
Publication date	Aug 13, 2020
Grant date	—

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.

First claim

1 . A semiconductor structure comprising a memory die bonded to a logic die, the memory die comprising:
an alternating stack of insulating layers and electrically conductive layers; memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film; a dielectric material portion in contact with sidewalls of the alternating stack; and a source layer comprising a first conductive material and electrically connected to end portions of the vertical semiconductor channels that are distal from an interface between the logic die and the memory die.

2 . The semiconductor structure of claim 1 , wherein:
the vertical semiconductor channels comprise a semiconductor material having a doping of a first conductivity type; and the source layer comprises a doped semiconductor material having a doping of a second conductivity type that is an opposite of the first conductivity type.

3 . The semiconductor structure of claim 1 , further comprising source cap regions including a doped semiconductor material portion having a doping of the second conductivity type and located directly on an end portion of a respective one of the vertical semiconductor channels, wherein the source layer contacts each of the source cap regions.

4 . The semiconductor structure of claim 1 , further comprising:
a pass-through via structure having a vertical extent that is greater than a vertical thickness of the alternating stack and vertically extending through the dielectric material portion; and a connection pad comprising a second conductive material that is different from the first conductive material, contacting a distal surface of the pass-through via structure, and electrically isolated from the source layer.

5 . The semiconductor structure of claim 4 , wherein the second conductive material comprises a metallic material.

6 . The semiconductor structure of claim 5 , wherein:
the connection pad comprises a pad barrier liner comprising a metallic barrier material and contacting a distal horizontal surface of the dielectric material portion, and a pad metal portion comprising the metallic material and contacting the pad barrier liner; and the pass-through via structure comprises a metallic barrier layer in contact with the pad barrier liner and a sidewall of the dielectric material portion, and a metallic fill material portion that is spaced from the connection pad and from the dielectric material portion by the metallic barrier layer.

7 . The semiconductor structure of claim 6 , wherein a distal portion of the metallic barrier layer protrudes from a horizontal interface between the dielectric material portion and the connection pad and into the connection pad, and is laterally surrounded by the connection pad.

8 . The semiconductor structure of claim 4 , further comprising a backside bonding pad located over the dielectric material portion, contacting a distal surface of the connection pad, and electrically isolated from the source layer.

9 . The semiconductor structure of claim 8 , further comprising at least one backside dielectric layer, wherein the backside bonding pad is located on a distal surface of the at least one backside dielectric layer, wherein the backside bonding pad comprises a via portion that extends through the at least one backside dielectric layer.

10 . The semiconductor structure of claim 4 , further comprising a bonding wire contacting a distal surface of the connection pad, and electrically isolated from the source layer.

11 . The semiconductor structure of claim 1 , wherein distal surfaces of the memory films are located within a horizontal plane including a horizontal interface between the source layer and the alternating stack or are more proximal to the interface between the logic die and the memory die than the interface between the source layer and the alternating stack is to the interface between the logic die and the memory die.

12 . The semiconductor structure of claim 11 , wherein interfaces between a semiconductor material of the vertical semiconductor channels and the source layer protrude from the horizontal plane including the horizontal interface between the source layer and the alternating stack along a vertical direction that points away from the interface between the logic die and the memory die.

13 . The semiconductor structure of claim 1 , wherein the logic die comprises a peripheral circuitry configured to operate memory elements in the memory stack structures and to drive the electrically conductive layers.

14 . A method of forming a semiconductor structure, comprising:
forming a memory die over a carrier substrate, wherein the memory die comprises memory stack structures that vertically extend through an alternating stack of insulating layers and electrically conductive layers, a dielectric material portion that contacts sidewalls of the alternating stack, and a pass-through via structure that vertically extends through the dielectric material portion, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film; physically exposing a distal end of each of the vertical semiconductor channels and a distal end of the pass-through via structure after removing the carrier substrate; forming a source layer comprising a first conductive material directly on a semiconductor material of the distal end of each of the vertical semiconductor channels; and forming a connection pad comprising a second conductive material that is different from the first conductive material directly on the pass-through via structure and the dielectric material portion, wherein the connection pad is electrically isolated from the source layer.

15 . The method of claim 14 , wherein:
the vertical semiconductor channels comprise a semiconductor material having a doping of a first conductivity type; and the first conductive material comprises a doped semiconductor material having a doping of a second conductivity type that is an opposite of the first conductivity type.

16 . The method of claim 15 , wherein:
the second conductive material comprises a metallic material; and the method comprises removing a first portion of the metallic material that overlies the source layer without removing a second portion of the metallic material from above the pass-through via structure, wherein the connection pad comprises the second portion of the metallic material.

17 . The method of claim 15 , wherein:
the second conductive material comprises a metallic material; and the method comprises patterning the metallic material into a first portion of the metallic material that overlies the source layer and a second portion of the metallic material located over the pass-through via structure.

18 . The method of claim 14 , further comprising:
patterning the first conductive material to form a first conductive material layer contacting the semiconductor material of the distal end of each of the vertical semiconductor channels; forming a backside isolation dielectric layer over the first conductive material layer and over the pass-through via structure; and forming an opening through the backside isolation dielectric layer, wherein a distal surface of the pass-through via structure is physically exposed.

19 . The method of claim 18 , wherein:
the second conductive material is deposited on the distal surface of the pass-through via structure through th

Assignees

• Sandisk Technologies Llc

Inventors

• Okina Teruo
• Nishida Akio
• Kai James

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title