Semiconductor device and solid-state imaging device

Patent metadata

Field	Value
Publication number	US-10026769-B2
Application number	US-201415023783-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Oct 4, 2013
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first substrate, including:
a first wiring layer, wherein first wiring layer includes a first metal pad, a second metal pad, and a third metal pad, and wherein the first metal pad is disposed at a light incident surface side of the first substrate as compared to the second metal pad and the third metal pad; and
a first insulating film, wherein a portion of the first insulating film is disposed between the second metal pad and the third metal pad in a cross-section view; and

a second substrate, including:
a second wiring layer, wherein the second wiring layer includes a fourth metal pad and a fifth metal pad; and
a second insulating film,
wherein a portion of the second insulating film is disposed between the fourth metal pad and the fifth metal pad in the cross-section view,
wherein the second substrate is bonded to the first substrate,
wherein the second metal pad and the fourth metal pad are bonded to each other at a bonding surface of the first and second substrates,
wherein the third metal pad and the fifth metal pad are bonded to each other at the bonding surface of the first and second substrates,
wherein the portion of the first insulating film and the portion of the second insulating film are bonded to each other at the bonding surface of the first and second substrates,
wherein the first metal pad overlaps the portion of the first insulating film in the cross-section view,
wherein the first metal pad overlaps the portion of the second insulating film in the cross-section view,
wherein a first edge of the first metal pad overlaps a portion of the second metal pad in the cross-section view,
wherein a second edge of the first metal pad overlaps a portion of the third metal pad in the cross-section view,
wherein the first edge of the first metal pad overlaps a portion of the fourth metal pad in the cross-section view,
wherein the second edge of the first metal pad overlaps a portion of the fifth metal pad in the cross-section view, and
wherein first and second edges of the second metal pad overlap the fourth metal pad in the cross-section view.

2. The semiconductor device according to claim 1 , wherein the first metal pad is a pad for wire bonding or probing.

3. The semiconductor device according to claim 1 , wherein the first metal pad includes Cu or Al.

4. The semiconductor device according to claim 1 , wherein the first, second, third, fourth, and fifth metal pads include Cu.

5. The semiconductor device according to claim 1 , wherein a region that does not contain a metal pad is provided at a center portion of a bonding-surface-side surface of the first metal wiring layer on the bonding surface of the first substrate and the second substrate.

6. The semiconductor device according to claim 1 , wherein the first substrate includes a first Si substrate and the second substrate includes a second Si substrate.

7. The semiconductor device according to claim 1 , wherein the second and third metal pads overlap at least a corner of the first metal pad.

8. The semiconductor device according to claim 1 , wherein the second and third metal pads overlap at least a side of the first metal pad.

9. The semiconductor device according to claim 1 , wherein the second and third metal pads are electrically connected to the first metal pad via a portion of the first wiring layer provided in addition to the first, second, and third metal pads.

10. The semiconductor device according to claim 1 , wherein the first metal pad is disposed in a peripheral region of a pixel array unit.

11. The semiconductor device according to claim 10 , wherein the pixel array unit includes a photodiode and a transfer transistor in the first substrate.

12. The semiconductor device according to claim 10 , wherein the pixel array unit includes an on-chip lens and a color filter above the first substrate.

13. The semiconductor device according to claim 10 , wherein the first wiring layer includes a sixth metal pad, wherein the second wiring layer includes a seventh metal pad, wherein the sixth metal pad of the first wiring layer and the seventh metal pad of the second wiring layer overlap the pixel array unit in the cross-section view, and the sixth metal pad and the seventh metal pad are bonded to each other at the bonding surface of the first substrate and the second substrate.

14. A solid-state imaging device comprising:
a first substrate, including:
a first wiring layer, wherein first wiring layer includes a first metal pad, a second metal pad, and a third metal pad, and wherein the first metal pad is disposed at a light incident surface side of the first substrate as compared to the second metal pad and the third metal pad; and
a first insulating film, wherein a portion of the first insulating film is disposed between the second metal pad and the third metal pad in a cross-section view; and

a second substrate, including:
a second wiring layer, wherein the second wiring layer includes a fourth metal pad and a fifth metal pad; and
a second insulating film,
wherein a portion of the second insulating film is disposed between the fourth metal pad and the fifth metal pad in the cross-section view,
wherein the second substrate is bonded to the first substrate,
wherein the second metal pad and the fourth metal pad are bonded to each other at a bonding surface of the first and second substrates,
wherein the third metal pad and the fifth metal pad are bonded to each other at the bonding surface of the first and second substrates,
wherein the portion of the first insulating film and the portion of the second insulating film are bonded to each other at the bonding surface of the first and second substrates,
wherein the first metal pad overlaps the portion of the first insulating film in the cross-section view,
wherein the first metal pad overlaps the portion of the second insulating film in the cross-section view,
wherein a first edge of the first metal pad overlaps a portion of the second metal pad in the cross-section view,
wherein a second edge of the first metal pad overlaps a portion of the third metal pad in the cross-section view,
wherein the first edge of the first metal pad overlaps a portion of the fourth metal pad in the cross-section view,
wherein the second edge of the first metal pad overlaps a portion of the fifth metal pad in the cross section view, and
wherein first and second edges of the second metal pad overlap the fourth metal pad in the cross-section view.

Assignees

• Sony Corp

Inventors

• Kagawa Yoshihisa
• Fujii Nobutoshi
• Fukasawa Masanaga
• Kaneguchi Tokihisa
• Hagimoto Yoshiya
• Aoyagi Kenichi
• Mitsuhashi Ikue

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title