Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding

Patent metadata

Field	Value
Publication number	US-10651153-B2
Application number	US-201816011139-A
Country	US
Kind code	B2
Filing date	Jun 18, 2018
Priority date	Jun 18, 2018
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.

First claim

What is claimed is:

1. A non-volatile storage device comprising:
a first die comprising a first three-dimensional (3D) array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry; and
a second die vertically stacked and bonded with the first die, the second die comprising a second 3D array of non-volatile storage cells, at least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die;
wherein the CMOS circuitry of the first die is disposed between the first 3D array of non-volatile storage cells and the second 3D array of non-volatile storage cells.

2. The non-volatile storage device of claim 1 , wherein:
the second die further comprises second CMOS circuitry to access the first and second 3D arrays of non-volatile storage cells.

3. The non-volatile storage device of claim 2 , wherein:
a portion of shared CMOS circuitry is included in the first CMOS circuitry of the first die and a remaining portion of the shared CMOS circuitry is included in the second CMOS circuitry of the second die, the shared CMOS circuitry including one or more of: charge pumps, static page buffers, IOs, control logic, and string drivers.

4. The non-volatile storage device of claim 3 , wherein:
the portion of the shared CMOS circuitry on the first die includes a first class of transistors, and the remaining portion of the shared CMOS circuitry on the second die includes a second class of transistors.

5. The non-volatile storage device of claim 4 , wherein:
the first class of transistors includes high voltage transistors and the second class of transistors includes low voltage transistors.

6. The non-volatile storage device of claim 2 , wherein:
shared string driver circuitry is to access both the first and second 3D arrays of non-volatile storage cells; and
a portion of the string driver circuitry for the first and second 3D arrays of non-volatile storage cells is included in the CMOS circuitry of the first die and a remaining portion of string driver circuitry is included in the second CMOS circuitry of the second die.

7. The non-volatile storage device of claim 2 , wherein:
layers of the first die are disposed in reverse order relative to the second die;
conductive contacts of the CMOS circuitry of the first die are bonded with conductive contacts of the second CMOS circuitry of the second die.

8. The non-volatile storage device of claim 2 , further comprising:
bonding pads between conductive contacts of the first CMOS circuitry and conductive contacts of the second CMOS circuitry.

9. The non-volatile storage device of claim 1 , further comprising:
a third die vertically stacked and bonded with the first or second die, the third die including a third 3D array of non-volatile storage cells, the CMOS circuitry of the first die to access the third 3D array of non-volatile storage cells.

10. A system comprising:
a processor; and
a non-volatile storage device coupled with the processor, the storage device comprising:
a first die comprising a first three-dimensional (3D) array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry to access the first 3D array of non-volatile storage cells; and
a second die vertically stacked and bonded with the first die, the second die comprising a second 3D array of non-volatile storage cells, the CMOS circuitry of the first die to access the second 3D array of non-volatile storage cells of the second die;
the CMOS circuitry of the first die is disposed between the first 3D array of non-volatile storage cells and the second 3D array of non-volatile storage cells.

11. The system of claim 10 , wherein:
the second die further comprises second CMOS circuitry to access the first and second 3D arrays of non-volatile storage cells.

12. The system of claim 11 , wherein:
a portion of shared CMOS circuitry is included in the first CMOS circuitry of the first die and a remaining portion of the shared CMOS circuitry is included in the second CMOS circuitry of the second die, the shared CMOS circuitry including one or more of: charge pumps, static page buffers, IOs, control logic, and string drivers.

13. The system of claim 12 , wherein:
the portion of the shared CMOS circuitry on the first die includes a first class of transistors, and the remaining portion of the shared CMOS circuitry on the second die includes a second class of transistors.

14. The system of claim 13 , wherein:
the first class of transistors includes high voltage transistors and the second class of transistors includes low voltage transistors.

15. The system of claim 11 , wherein:
shared string driver circuitry is to access both the first and second 3D arrays of non-volatile storage cells; and
a portion of the string driver circuitry for the first and second 3D arrays of non-volatile storage cells is included in the CMOS circuitry of the first die and a remaining portion of string driver circuitry is included in the second CMOS circuitry of the second die.

16. The system of claim 10 , further comprising:
a third die vertically stacked and bonded with the first or second die, the third die including a third 3D array of non-volatile storage cells, the CMOS circuitry of the first die to access the third 3D array of non-volatile storage cells.

17. A three-dimensional (3D) NAND memory device comprising:
a first die comprising a first three-dimensional (3D) array of non-volatile NAND memory cells and control circuitry; and
a second die vertically stacked and bonded with the first die, the second die comprising a second 3D array of non-volatile NAND memory cells, at least a portion of the control circuitry of the first die to access both the first 3D array of non-volatile NAND memory cells of the first die and the second 3D array of non-volatile NAND memory cells of the second die;
the control circuitry of the first die is disposed between the first 3D array of non-volatile NAND memory cells and the second 3D array of non-volatile NAND memory cells.

Assignees

• Intel Corp

Inventors

• Fastow Richard
• Hasnat Khaled
• Majhi Prashant
• Jungroth Owen

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H01L24/02

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic