Vertical-type memory device

Patent metadata

Field	Value
Publication number	US-2020098786-A1
Application number	US-201916378625-A
Country	US
Kind code	A1
Filing date	Apr 9, 2019
Priority date	Sep 21, 2018
Publication date	Mar 26, 2020
Grant date	—

Abstract

A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers. The upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs.

First claim

1 . A vertical-type memory device, comprising:
a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure; a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers; and a plurality of gate contact plugs penetrating the first interlayer insulating layer and respectively contacting the gate electrode layers, wherein the plurality of gate electrode layers comprise lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers so that the lower gate electrode layers are between the substrate and the upper gate electrode layers, and wherein the plurality of gate contact plugs comprise lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers, wherein the upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs.

2 . The vertical-type memory device of claim 1 , wherein:
the lower gate contact plugs are each integrally formed of a continuous material to extend from a respective lower gate electrode layer to a height above a top surface of the first interlayer insulating layer; and the upper gate contact plugs are each integrally formed of a continuous material to extend from a respective upper gate electrode layer to a height above a top surface of the first interlayer insulating layer.

3 . The vertical-type memory device of claim 2 , further comprising:
a plurality of contact studs respectively disposed on the lower gate contact plugs, wherein the top-most portions of the upper gate contact plugs are disposed at the same height as a height of top-most portions of the plurality of contact studs.

4 . The vertical-type memory device of claim 3 , further comprising:
first metal wires respectively disposed on and directly connected to the upper gate contact plugs and second metal wires respectively disposed on and directly connected to the plurality of contact studs.

5 . The vertical-type memory device of claim 4 , wherein the first metal wires are respectively integrated with the upper gate contact plugs.

6 . The vertical-type memory device of claim 2 , wherein the plurality of gate electrode layers forming the staircase structure have ends including pad regions having thicknesses greater than thicknesses of the other regions of the plurality of gate electrode layers, and the plurality of gate contact plugs contact the pad regions.

7 . The vertical-type memory device of claim 2 , further comprising:
a lower wiring structure disposed below the substrate; and through plugs penetrating through the plurality of gate electrode layers and contacting the lower wiring structure, wherein the top-most portions of the upper gate contact plugs are disposed at a height higher than a height of top surfaces of the through plugs.

8 . The vertical-type memory device of claim 2 , further comprising:
a plurality of channel structures penetrating through the plurality of gate electrode layers; and a plurality of dummy structures penetrating through at least one of the plurality of gate electrode layers, and disposed adjacently to the plurality of gate contact plugs.

9 . The vertical-type memory device of claim 8 , wherein the plurality of dummy structures have the same structure as a structure of the plurality of channel structures, and are electrically connected to the substrate.

10 . The vertical-type memory device of claim 8 , wherein the plurality of channel structures have a structure different from a structure of the plurality of dummy structures, the plurality of channel structures are electrically connected to the substrate, and the plurality of dummy structures are insulated from the substrate.

11 - 12 . (canceled)

13 . A vertical-type memory device, comprising:
a memory cell region comprising a plurality of gate electrode layers spaced apart from one another and vertically stacked on a substrate, and a plurality of gate contact plugs respectively contacting the plurality of gate electrode layers, wherein the plurality of gate contact plugs comprise a first gate contact plug contacting a lowermost gate electrode layer among the plurality of gate electrode layers, and a second gate contact plug contacting an uppermost gate electrode layer among the plurality of gate electrode layers, and the first gate contact plug has a top surface having a first height lower than a second height of a top-most portion of the second gate contact plug, wherein the first gate contact plug is integrally formed of a continuous material to extend from the lowermost gate electrode layer to a height above the uppermost gate electrode layer; and the second gate contact plug is integrally formed of a continuous material to extend from the uppermost gate electrode layer to the second height.

14 . The vertical-type memory device of claim 13 , further comprising:
a peripheral circuit region comprising circuit devices and lower wiring structures disposed on a lower substrate below the substrate, wherein the memory cell region is disposed on the peripheral circuit region.

15 . The vertical-type memory device of claim 13 , wherein the plurality of gate electrode layers extend by different lengths in a first direction and form a staircase structure, and further comprising:
a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, wherein the first gate contact plug penetrates the first interlayer insulating layer to contact the lowermost gate electrode layer, and the second gate contact plug penetrates the first interlayer insulating layer to contact the uppermost gate electrode layer.

16 . The vertical-type memory device of claim 13 , further comprising:
a through region penetrating through the substrate and the plurality of gate electrode layers; and a through plug penetrating through the through region and connected to a lower wiring structure disposed on a lower substrate below the substrate, wherein the through plug has a top surface having a height lower than the second height.

17 . The vertical-type memory device of claim 13 , wherein the memory cell region further comprises a contact stud disposed on the first gate contact plug, and the top-most portion of the second gate contact plug is disposed at the same height as a height of a top surface of the contact stud.

18 . The vertical-type memory device of claim 13 , wherein the plurality of gate electrode layers include pad regions and other regions, the pad regions having thicknesses greater than thicknesses of the other regions, and for each gate electrode layer including the lowermost gate electrode layer and uppermost gate electrode layer, a respective gate contact plug contacts a respective pad region.

19 . The vertical-type memory device of claim 13 , further comprising:
a plurality of working channel structures penetrating through the plurality of gate electrode layers; and a plurality of dummy channel structures penetrating through at least one of the plurality of gate electrode layers.

20 . The vertical-type memory device of claim 19 , wherein the plurality of working channel structures have structures different from the plurality of dummy channel structures, the plurality of working channel str

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Joo Won
• Park Kyeong Jin

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/11573

  Electricity · mapped topic

• H01L29/4234

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L23/481

  Electricity · mapped topic