Semiconductor device

Patent metadata

Field	Value
Publication number	US-11842964-B2
Application number	US-202117323407-A
Country	US
Kind code	B2
Filing date	May 18, 2021
Priority date	Aug 18, 2020
Publication date	Dec 12, 2023
Grant date	Dec 12, 2023

Abstract

A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having an active region;
a plurality of standard cells on the active region of the substrate, the plurality of standard cell arranged in a plurality of rows, the plurality of rows extending in a first direction, the plurality of standard cells each including
an active pattern extending in the first direction, a gate structure intersecting the active pattern and extending in a second direction that intersects the first direction,
a plurality of source/drain regions in the active pattern with one of the plurality of source/drain regions on one side of the gate structure and another of the plurality of source/drain regions on another side of the gate structure, and
contact structures respectively connected to the source/drain regions and extending in a third direction that is perpendicular to an upper surface of the substrate; and

a plurality of power lines respectively extending in the first direction along boundaries of the plurality of standard cells, the plurality of power lines configured to supply power to the plurality of standard cells,
wherein each of the plurality of standard cells further includes a plurality of wiring lines extending in the first direction and arranged in the second direction, and
at least some wiring lines of the plurality of wiring liners in at least one standard cell among the plurality of standard cells are arranged such that at least one of a pitch, a spacing, or a line width is different from a respective one of a pitch, a spacing, or a line width of a neighboring standard cell.

2. The semiconductor device of claim 1 , wherein the at least some of the plurality of wiring lines have the same line width.

3. The semiconductor device of claim 1 , wherein the at least some of the plurality of wiring lines have different line widths.

4. The semiconductor device of claim 1 , wherein
each of the plurality of standard cells has a first conductivity-type device area and a second conductivity-type device area, the first conductivity-type device are arranged in the second direction with respect to the second conductivity-type device area, and
standard cells of two adjacent rows among the plurality of rows are arranged such that same conductivity-type device areas are adjacent to each other.

5. The semiconductor device of claim 4 , wherein in the at least one standard cell, two wiring lines adjacent to a center of the plurality of wiring lines have a spacing greater than a spacing between other neighboring wiring lines of the plurality of wiring lines.

6. The semiconductor device of claim 4 , wherein the plurality of wiring lines in the at least one standard cell are arranged symmetrically with respect to a central line that extends in the first direction.

7. The semiconductor device of claim 1 , wherein at least one of the plurality of standard cells has numbers of wiring lines different from a number of wiring lines of other standard cells of the plurality of standard cells located in the same row.

8. The semiconductor device of claim 1 , wherein at least one of the plurality of standard cells includes first neighboring wiring lines of the at least some neighboring wiring lines which are arranged such that at least one of a pitch, a spacing, or a line width is different from second neighboring wiring lines of the at least some neighboring wiring lines of other standard cells located in the same row.

9. The semiconductor device of claim 1 , wherein the plurality of standard cells include a first group of standard cells arranged in a first row and having a first height defined in the second direction, and a second group of standard cells arranged in a second row and having a second height defined in the second direction, the second height being different from the first height.

10. The semiconductor device of claim 9 , wherein the plurality of power lines include a shared power line shared by the first group of standard cells and the second group of standard cells, the shared power line being shared at a boundary between the first group of standard cells and the second group of standard cells.

11. The semiconductor device of claim 9 , wherein the plurality of power lines further include a conductive via on a level above an upper surface of the contact structure, the conductive via connecting the plurality of power lines and the contact structure.

12. The semiconductor device of claim 11 , further comprising:
a dummy pattern on the active region, the dummy pattern between the first group of standard cells and the second group of standard cells, the dummy pattern extending in the first direction.

13. The semiconductor device of claim 9 , wherein the plurality of power lines include a buried power line buried in the active region, and the contact structure has an extension portion extending in the second direction and connected to the buried power line.

14. The semiconductor device of claim 13 , further comprising:
a conductive via connecting the contact structure to at least one wiring line among the plurality of wiring lines, the contact structure being connected to the buried power line.

15. The semiconductor device of claim 13 , wherein the at least some neighboring wiring lines of the plurality of wire lines of two standard cells adjacent to the buried power line in the second direction, among the plurality of standard cells, are arranged at a same pitch and/or at a same spacing.

16. A semiconductor device comprising:
a substrate having an active region;
a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction;
a second group of standard cells arranged in a second row on the active region of the substrate, the second group of standard cells having a second height defined in the column direction, the second height different from the first height; and
a plurality of power lines extending in a row direction and respectively extending along boundaries of the first group of standard cells and the second group of standard cells,
wherein the first and second groups of standard cells each include a plurality of wiring lines extending in the row direction and arranged in the column direction, and
at least some wiring lines of the plurality of wiring lines in at least one standard cell of the first group is arranged such that at least one of a pitch, a spacing, or a line width is different from a respective one of a pitch, a spacing, or a line width of a neighboring standard cell of the second groups of standard cells.

17. The semiconductor device of claim 16 , further comprising:
an extended standard cell arranged over the first row and the second row and having a height corresponding to a sum of the first height and the second height.

18. The semiconductor device of claim 16 , wherein the plurality of wiring lines include first wiring lines arranged on a same level as a level of the plurality of power lines.

19. The semiconductor device of claim 18 , wherein the plurality of wiring lines further include second wiring lines arranged on a level above a level of the plurality of power lines.

20. A semiconductor device comprising:
a substrate having an active region;
a plurality of standard cells on the active region of the substrate, the plurality of standard cells arranged in a plurality of rows extending in a first direction, the plurality of standard cells each including an active pattern extending in the first direction, a ga

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jungho
• Baek Sanghoon

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title