Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices

Patent metadata

Field	Value
Publication number	US-11837604-B2
Application number	US-202117481353-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Sep 22, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

An approach provides a semiconductor structure with a first crystalline surface orientation and a first nanosheet stack on the semiconductor substrate with the first crystalline surface orientation. The semiconductor substrate structure includes a second nanosheet stack with a second crystalline surface orientation above the first nanosheet stack, wherein the first nanosheet stack and the second nanosheet stack are separated by a dielectric material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate with a first crystalline surface orientation;
a first type field-effect transistor directly on the semiconductor substrate and directly under a dielectric material contacting a second type field-effect transistor, wherein the first type field-effect transistor with the first crystalline surface orientation in a first plurality of nanosheet channels; and
the second type field-effect transistor directly on the dielectric material with a second crystalline surface orientation in a second plurality of nanosheet channels, wherein the second plurality of nanosheet channels are parallel to the semiconductor substrate.

2. The semiconductor device of claim 1 , wherein the first field-effect transistor and the second field-effect transistor are each a horizontal gate-all-around devices.

3. The semiconductor device of claim 1 , wherein the first type field-effect transistor is a p-type field-effect transistor with a {110} crystalline surface orientation in the first plurality of nanosheet channels.

4. The semiconductor device of claim 1 , wherein the first type field-effect transistor is an n-type field-effect transistor with a {100} crystalline surface orientation in the second plurality of nanosheet channels.

5. The semiconductor device of claim 1 , wherein the first type field-effect transistor and the second type field-effect transistor are vertically stacked.

6. The semiconductor device of claim 1 , wherein the second type field-effect transistor is a field-effect transistor selected from the group consisting of a p-type field-effect transistor and an n-type field-effect transistor.

7. The semiconductor device of claim 6 , wherein the second type field-effect transistor is a field-effect transistor selected from the group consisting of a p-type field-effect transistor and an n-type field-effect transistor.

8. The semiconductor device of claim 7 , wherein the second type field-effect transistor is the p-type field-effect transistor and the first type field-effect transistor is the n-type field-effect transistor.

9. The semiconductor device of claim 1 , wherein the first type field-effect transistor and the second type field-effect transistor are a complementary metal-oxide-semiconductor device (CMOS) device.

10. The semiconductor device of claim 1 , wherein the first crystalline surface orientation is selected from the group consisting of a {110} crystalline surface orientation and a {100} crystalline surface orientation.

11. The semiconductor device of claim 6 , wherein the first type field-effect transistor is the p-type field-effect transistor, further comprising:
the p-type transistor is directly on the semiconductor substrate with a {110} crystalline surface orientation;
the dielectric material is directly on the p-type field-effect transistor; and
the second type field-effect transistor is directly on the dielectric material, wherein the second type field-effect transistor is the n-type field-effect transistor with a {100} crystalline surface orientation in the first plurality of nanosheet channels.

12. The semiconductor device of claim 6 , wherein the first type field-effect transistor is the n-type field-effect transistor, further comprising:
the n-type transistor is directly on the semiconductor substrate with a {100} crystalline surface orientation;
the dielectric material is directly on the n-type field-effect transistor; and
the second type field-effect transistor is directly on the dielectric material, wherein the second type field-effect transistor is the n-type field-effect transistor with a {100} crystalline surface orientation in the first plurality of nanosheet channels.

13. The semiconductor device of claim 1 , wherein the semiconductor substrate, the first plurality of nanosheet channels, and the second plurality of nanosheet channels are vertically aligned and parallel.

14. The semiconductor device of claim 1 , wherein the semiconductor substrate with the first crystalline surface orientation is composed of a single semiconductor material layer.

Assignees

• IBM
• Int Business Machine Corporation

Inventors

• Cheng Kangguo
• Mochizuki Shogo
• Li Juntao

Classifications

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title