Strained stacked nanosheet FETS and/or quantum well stacked nanosheet

Patent metadata

Field	Value
Publication number	US-9711414-B2
Application number	US-201514887484-A
Country	US
Kind code	B2
Filing date	Oct 20, 2015
Priority date	Oct 21, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

First claim

We claim:

1. A method for fabricating a biaxially strained nanosheet, the method comprising:
growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties;
in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer;
selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and
selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

2. The method of claim 1 , further comprising: after the first and second sacrificial material layers are selectively etched, depositing materials in regions where the first and second sacrificial material layers were selectively etched away, maintaining the biaxial strain in the active layers.

3. The method of claim 2 , wherein depositing the materials further comprises: depositing a first gate stack in regions where the first sacrificial material layers were selectively etched away, the first gate stack capable of maintaining the biaxial strain.

4. The method of claim 3 , wherein depositing the materials further comprises depositing a second gate stack in regions where the second sacrificial material layers were selectively etched away.

5. The method of claim 3 , wherein the biaxially strained nanosheet is tensile-strained.

6. The method of claim 5 , wherein the biaxially strained nanosheet comprises a first field effect transistor (FET) type of a CMOS nanosheet FET circuit.

7. The method of claim 3 , wherein the biaxially strained nanosheet is compressively-strained.

8. The method of claim 7 , wherein the biaxially strained nanosheet comprises a second FET type of a CMOS nanosheet FET circuit.

9. The method of claim 3 , wherein a width of the biaxially strained nanosheet ranges from 5-50 nm, a thickness of the biaxially strained nanosheet ranges from 2-10 nm, the vertical spacing between two biaxially strained nanosheets ranges from 5-20 nm, and the horizontal spacing between the biaxially strained nanosheets ranges from 5-20 nm.

10. The method of claim 9 , wherein the width of the biaxially strained nanosheet ranges from 10-40 nm, the thickness of the biaxially strained nanosheet ranges from 4-7 nm, the vertical spacing between two of the biaxially strained nanosheets ranges from 7-15 nm, and the horizontal spacing between the biaxially strained nanosheets ranges from 7-15 nm.

11. The method of claim 4 , wherein the first gate stack comprises first gate dielectric materials and first metal materials, and the second gate stack comprises second gate dielectric materials and second metal materials.

12. The method of claim 11 , wherein the first gate stack is substantially the same as the second gate stack.

13. The method of claim 11 , wherein the first gate stack is different from the second gate stack.

14. The method of claim 11 , wherein the first gate stack has a first effective workfunction and the second gate stack has a second effective workfunction.

15. The method of claim 11 , wherein a separation of the first metal material and the second metal material in at least one region of a nanosheet FET structure is larger than a separation of the first metal material and the second metal material from a first surface and second surface of the nanosheet, respectively.

16. The method of claim 15 , wherein the separation of the first metal material and second metal material in the at least one reason region of the nanosheet FET comprises adjacent layers of first gate dielectric materials and second gate dielectric materials.

17. The method of claim 11 , wherein the first metal material and second metal material are connected together in at least one region of a nanosheet FET structure.

18. The method of claim 11 , wherein the first metal material and second metal material are not connected together in at least one region of a nanosheet FET structure.

19. The method of claim 1 , wherein the active material layers are at least one of i) silicon, ii) silicon and germanium, and iii) germanium.

20. The method of claim 19 , wherein one of the first and second sacrificial material layers are a III-V alloy, and the other sacrificial material layers are a different, chemically dissimilar III-V alloy.

21. The method of claim 19 , wherein one of the first and second sacrificial material layers are a III-V alloy, and the other sacrificial material layers are a different, chemically dissimilar II-VI alloy.

22. The method of claim 19 , wherein one of the first and second sacrificial material layers are a II-VI alloy, and the other sacrificial material layers are a different, chemically dissimilar II-VI alloy.

23. The method of claim 1 , wherein the active material layers are a III-V alloy.

24. The method of claim 23 , wherein the first sacrificial material layers are a different III-V alloy than the active material layers and the second sacrificial material layers are a different III-V alloy from the active material layers and the first sacrificial material layers, wherein each of the III-V alloys are chemically dissimilar in order to allow for highly selective etches.

25. The method of claim 23 , wherein one of the first and second sacrificial material layers are a different III-V alloy than the active material layers and the other sacrificial material layers are a II-VI alloy, wherein each of the III-V alloys are chemically dissimilar in order to allow for highly selective etches.

26. The method of claim 23 , wherein one of the first and second sacrificial material layers are a II-VI alloy and the other sacrificial material layers are a different, chemically dissimilar II-VI alloy.

27. The method of claim 1 , wherein the active material layers are a II-VI alloy.

28. The method of claim 27 , wherein one of the first and second sacrificial material layers are a III-V alloy and the other sacrificial material layers are a different, chemically dissimilar III-V alloy.

29. The method of claim 27 , wherein one of the first and second sacrificial material layers are a different II-VI alloy than the active material layers and the other sacrificial material layers are a III-V alloy, wherein each of the II-VI alloys are chemically dissimilar in order to allow for highly selective etches.

30. The method of claim 27 , wherein the first sacrificial material layers are a different II-VI alloy than the active material layers and the second sacrificial material layers are a different II-VI alloy from the active material layers and the first sacrificial material layers, wherein each of the II-VI alloys are chemically dissimilar in order to allow for highly selective etches.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hatcher Ryan M
• Bowen Robert C
• Rodder Mark S
• Obradovic Borna J
• Hong Joon Goo

Classifications

• H01L21/823828

  Electricity · mapped topic

• H01L29/0665

  Electricity · mapped topic

• H01L29/66484

  Electricity · mapped topic

• H01L29/7847

  Electricity · mapped topic

• H01L21/823807 Primary

  Electricity · mapped topic