CMOS nanowire structure

Patent metadata

Field	Value
Publication number	US-9583491-B2
Application number	US-201514948083-A
Country	US
Kind code	B2
Filing date	Nov 20, 2015
Priority date	Dec 23, 2011
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first semiconductor device comprising:
a first nanowire disposed above a substrate, the first nanowire having a mid-point a first distance above the substrate without an intervening nanowire between the first nanowire and the substrate, and the first nanowire comprising a discrete channel region and discrete source and drain regions on either side of the discrete channel region, wherein a portion of the first nanowire is non-discrete;
a first gate electrode stack completely surrounding the discrete channel region of the first nanowire;
a first pair of contacts completely surrounding the discrete source and drain regions of the first nanowire; and
a first pair of spacers disposed between the first gate electrode stack and the first pair of contacts; and

a second semiconductor device laterally adjacent to the first semiconductor device, the second semiconductor device comprising:
a second nanowire disposed above the substrate without an intervening nanowire between the second nanowire and the substrate, the second nanowire having a mid-point a second distance above the substrate, and the second nanowire comprising a discrete channel region and discrete source and drain regions on either side of the discrete channel region, wherein the first distance is different from the second distance, wherein a portion of the second nanowire is non-discrete;
a second gate electrode stack completely surrounding the discrete channel region of the second nanowire;
a second pair of contacts completely surrounding the discrete source and drain regions of the second nanowire; and
a second pair of spacers disposed between the second gate electrode stack and the second pair of contacts.

2. The semiconductor structure of claim 1 , wherein the first nanowire consists essentially of a material selected from the group consisting of silicon, strained silicon, silicon germanium (Si x Ge y , where 0<x<100, and 0<y<100), silicon carbide, carbon doped silicon germanium and a group III-V compound, and wherein the second nanowire consists essentially of a different material selected from the group consisting of silicon, strained silicon, silicon germanium (Si x Ge y , where 0<x<100, and 0<y<100), carbon doped silicon germanium and a group III-V compound.

3. The semiconductor structure of claim 2 , wherein the first semiconductor device is an NMOS device, and the second semiconductor device is a PMOS device.

4. The semiconductor structure of claim 1 , wherein the first and second nanowires are disposed above a bulk crystalline substrate having an intervening dielectric layer disposed thereon.

5. The semiconductor structure of claim 1 , wherein the first and second nanowires are disposed above a bulk crystalline substrate having no intervening dielectric layer disposed thereon.

6. A method of fabricating a semiconductor structure, the method comprising:
forming a first semiconductor device comprising a first nanowire formed above a substrate, the first nanowire having a mid-point a first distance above the substrate without an intervening nanowire between the first nanowire and the substrate, and the first nanowire comprising a discrete channel region and discrete source and drain regions on either side of the discrete channel region, and comprising a first gate electrode stack completely surrounding the discrete channel region of the first nanowire, and comprising a first pair of contacts completely surrounding the discrete source and drain regions of the first nanowire, wherein a portion of the first nanowire is non-discrete;
forming a first pair of spacers between the first gate electrode stack and the first pair of contacts;
forming a second semiconductor device laterally adjacent to the first semiconductor device, the second semiconductor device comprising a second nanowire formed above the substrate without an intervening nanowire between the second nanowire and the substrate, the second nanowire having a mid-point a second distance above the substrate, and the second nanowire comprising a discrete channel region and discrete source and drain regions on either side of the discrete channel region, wherein the first distance is different from the second distance, and comprising a second gate electrode stack completely surrounding the discrete channel region of the second nanowire, and comprising a second pair of contacts completely surrounding the discrete source and drain regions of the second nanowire, wherein a portion of the second nanowire is non-discrete; and
forming a second pair of spacers between the second gate electrode stack and the second pair of contacts.

7. The method of claim 6 , wherein the first nanowire consists essentially of a material selected from the group consisting of silicon, strained silicon, silicon germanium (Si x Ge y , where 0<x<100, and 0<y<100), silicon carbide, carbon doped silicon germanium and a group III-V compound, and wherein the second nanowire consists essentially of a different material selected from the group consisting of silicon, strained silicon, silicon germanium (Si x Ge y , where 0<x<100, and 0<y<100), carbon doped silicon germanium and a group III-V compound.

8. The method of claim 6 , wherein the first semiconductor device is an NMOS device, and the second semiconductor device is a PMOS device.

9. The method of claim 6 , wherein the first and second nanowires are formed above a bulk crystalline substrate having an intervening dielectric layer formed thereon.

10. The method of claim 6 , wherein the first and second nanowires are formed above a bulk crystalline substrate having no intervening dielectric layer formed thereon.

11. A semiconductor structure, comprising:
a first semiconductor device comprising:
a first nanowire disposed above a substrate, the first nanowire having a mid-point a first distance above the substrate without an intervening nanowire between the first nanowire and the substrate, and the first nanowire comprising a discrete channel region and discrete source and drain regions on either side of the discrete channel region, wherein a portion of the first nanowire is non-discrete;
a first gate electrode stack completely surrounding the discrete channel region of the first nanowire;
a first pair of contacts completely surrounding the discrete source and drain regions of the first nanowire; and

a second semiconductor device laterally adjacent to the first semiconductor device, the second semiconductor device comprising:
a second nanowire disposed above the substrate without an intervening nanowire between the second nanowire and the substrate, the second nanowire having a mid-point a second distance above the substrate, and the second nanowire comprising a discrete channel region and discrete source and drain regions on either side of the discrete channel region, wherein the first distance is different from the second distance, wherein a portion of the second nanowire is non-discrete;
a second gate electrode stack completely surrounding the discrete channel region of the second nanowire; and
a second pair of contacts completely surrounding the discrete source and drain regions of the second nanowire.

12. The semiconductor structure of claim 11 , wherein the first nanowire consists essentially of a material selected from the group consisting of silicon, strained silicon, silicon germanium (Si x Ge y , where 0<x<100, and 0<y<100), silicon carbide, carbon doped silicon germanium and a group III-V compound, and wherein the second nanowire consists essentially of a different material selected from the group consisting of silicon, strained silicon, silicon germanium (Si

Assignees

• Kim Seiyon
• Kuhn Kelin J
• Ghani Tahir
• Murthy Anand S
• Cappellani Annalisa
• Cea Stephen M
• Rios Rafael
• Glass Glenn A
• Intel Corp

Inventors

• Kim Seiyon
• Kuhn Kelin J
• Ghani Tahir
• Murthy Anand S
• Cappellani Annalisa
• Cea Stephen M
• Rios Rafael
• Glass Glenn A

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/775

  Electricity · mapped topic

• H01L29/0676

  Electricity · mapped topic

• H01L29/66439

  Electricity · mapped topic

• H01L21/823828

  Electricity · mapped topic