Dual channel material for finFET for high performance CMOS

Patent metadata

Field	Value
Publication number	US-9917015-B2
Application number	US-201715424416-A
Country	US
Kind code	B2
Filing date	Feb 3, 2017
Priority date	Aug 27, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion.

First claim

What is claimed as new is:

1. A method of forming a semiconductor structure comprising:
forming a plurality of silicon fins extending upwards from a bulk silicon portion, wherein each silicon fin of said plurality of silicon fins is separated by a trench isolation region;
recessing a predetermined number of silicon fins of said plurality of silicon fins to provide a plurality of silicon fin portions in an nFET device region and a pFET device region of said bulk silicon portion;
forming a relaxed silicon germanium alloy fin portion on a topmost surface of each silicon fin portion;
forming, in any order, a compressively strained silicon-containing germanium alloy fin portion on a topmost surface of each relaxed silicon germanium alloy fin portion in said pFET device region and a tensile strained silicon-containing fin portion on a topmost surface of each relaxed silicon germanium alloy fin portion in said nFET device region; and
recessing each trench isolation region to provide trench isolation structures and to partially expose sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile stained silicon fin portion, wherein some of said silicon fins are non-recessed and each of said non-recessed silicon fins has a topmost surface that is coplanar with a topmost surface of each of said compressively strained silicon-containing germanium alloy fin portion and said tensile strained silicon-containing fin portion, and wherein a low leakage functional gate structure is formed on exposed sidewall surfaces and said topmost surface of each of said non-recessed silicon fin.

2. The method of claim 1 , wherein said forming said plurality of silicon fins extending upwards from said bulk silicon portion comprises:
providing a structure including, from bottom to top, a hard mask layer and a bulk silicon substrate;
forming a plurality of trenches in said hard mask layer and said bulk silicon substrate; and
filling each of said trenches with a trench dielectric material.

3. The method of claim 2 , wherein prior to performing said etching process, a block mask is formed on some of the silicon fins in a region of the bulk silicon portion other than said nFET device region and said pFET device region.

4. The method of claim 1 , wherein said recessing said predetermined number of silicon fins of said plurality of silicon fins comprises an etching process.

5. The method of claim 1 , wherein said forming said relaxed silicon germanium alloy fin portion comprises an epitaxial semiconductor regrowth process.

6. The method of claim 5 , wherein each relaxed silicon germanium alloy fin portion comprises a lower portion having a first defect density and an upper portion having a second defect density that is less than the first defect density.

7. The method of claim 1 , wherein said forming the compressively strained silicon-containing germanium alloy fin portion is performed prior to forming said tensile strained silicon-containing fin portion and a block mask is used to protect the nFET device region during said forming of said compressively strained silicon-containing germanium alloy fin portion.

8. The method of claim 1 , wherein said forming the tensile strained silicon-containing fin portion is performed prior to forming said compressively strained silicon-containing germanium alloy fin portion and a block mask is used to protect the pFET device region during said forming of said tensile strained silicon-containing fin portion.

9. The method of claim 1 , wherein said forming said compressively strained silicon-containing germanium alloy fin portion comprises an epitaxial deposition process and said forming said tensile strained silicon-containing fin portion comprises another epitaxial deposition process.

10. The method of claim 1 , further comprising forming a functional gate structure on exposed sidewall surfaces and a topmost surface of said compressively strained silicon-containing germanium alloy fin portion, and forming another functional gate structure on exposed sidewall surfaces and a topmost surface of said tensile strained silicon-containing fin portion.

11. The method of claim 2 , wherein after forming said compressively strained silicon-containing germanium alloy fin portion and said forming said tensile strained silicon-containing fin portion, said block mask is removed to expose another predetermined number of silicon fins, and wherein after said recessing said trench isolation structures, a further functional gate structure is formed on exposed sidewall surfaces and a topmost surface of each silicon fin.

12. The method of claim 1 , wherein said compressively strained silicon-containing germanium alloy fin portion, said relaxed silicon germanium alloy fin portion and said silicon fin portions in said pFET device region have sidewall surfaces that are vertically coincident to each other.

13. The method of claim 1 , wherein said tensile strained silicon-containing fin portion, said relaxed silicon germanium alloy fin portion, and said silicon fin portions in said nFET device region have sidewall surfaces that are vertically coincident to each other.

14. The method of claim 1 , wherein each relaxed silicon germanium alloy fin portion contains threading dislocations.

15. The method of claim 14 , wherein said threading dislocations in each of said relaxed silicon germanium alloy fin portions terminate at a sidewall of one of said trench isolation structures.

16. The method of claim 1 , wherein each relaxed silicon germanium alloy fin portion has a relaxation value of 90% or greater, and a germanium content of 20 atomic percent or greater.

17. The method of claim 1 , wherein said compressively strained silicon-containing germanium alloy fin portion contains a greater amount of germanium than said relaxed silicon germanium alloy fin portion in said pFET device region.

18. The method of claim 1 , wherein said tensile strained silicon-containing fin portion consists of unalloyed silicon.

19. The method of claim 1 , wherein said tensile strained silicon-containing fin portion consists of a silicon germanium alloy having a germanium content that is less than a germanium content of said relaxed silicon germanium alloy fin portion in said nFET device region.

20. A method of forming a semiconductor structure comprising:
forming a plurality of silicon fins extending upwards from a bulk silicon portion, wherein each silicon fin of said plurality of silicon fins is separated by a trench isolation region;
recessing a predetermined number of silicon fins of said plurality of silicon fins to provide a plurality of silicon fin portions in an nFET device region and a pFET device region of said bulk silicon portion;
forming a relaxed silicon germanium alloy fin portion on a topmost surface of each silicon fin portion;
forming, in any order, a compressively strained silicon-containing germanium alloy fin portion on a topmost surface of each relaxed silicon germanium alloy fin portion in said pFET device region and a tensile strained silicon-containing fin portion on a topmost surface of each relaxed silicon germanium alloy fin portion in said nFET device region; and
recessing each trench isolation region to provide trench isolation structures and to partially expose sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile stained silicon fin portion, wherein said tensile strained silicon-containing fin portion consists of a silicon germanium a

Assignees

• IBM

Inventors

• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/823878

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic