Full package vapor chamber with IHS

Patent metadata

Field	Value
Publication number	US-11832419-B2
Application number	US-201916723865-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Dec 20, 2019
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a die on a package substrate;
an integrated heat spreader (IHS) over the die and the package substrate, wherein the IHS has a lid and a plurality of sidewalls;
a sealant that couples the plurality of sidewalls of the IHS to the package substrate; and
a layer below the lid of the IHS, wherein the layer is over the die and a top surface of the package substrate, and wherein the layer is on a bottom surface of the lid of the IHS and an interior surface of the plurality of sidewalls of the IHS, wherein a vapor chamber is defined by the top surface of the package substrate, the bottom surface of the lid of the IHS, and the interior surface of the plurality of sidewalls of the IHS, and wherein the bottom surface of the lid of the IHS is exposed to the vapor chamber.

2. The semiconductor package of claim 1 , wherein the vapor chamber is hermetically sealed with the sealant between the top surface of the package substrate and the plurality of sidewalls of the IHS, and wherein the vapor chamber has a vapor space defined by a surface of the layer and the bottom surface of the lid of the IHS.

3. The semiconductor package of claim 2 , wherein the layer is over a surface of the die, wherein the layer is comprised of one or more wick materials, wherein the one or more wick materials include one or more porous materials, and wherein the one or more porous materials include metals, powders, or graphite.

4. The semiconductor package of claim 3 , wherein the bottom surface of the lid of the IHS faces the top surface of the package substrate and the surface of the die, and wherein the interior surface of the plurality of sidewalls of the IHS faces the surface of the die.

5. The semiconductor package of claim 3 , wherein the layer thermally couples the surface of the die to the bottom surface of the lid of the IHS.

6. The semiconductor package of claim 3 , further comprising:
a hydrophobic layer on the surface of the die and the top surface of the package substrate, wherein the hydrophobic layer is between the layer and the surface of the die, and wherein the hydrophobic layer is between the layer and the top surface of the package substrate;
a liquid in the vapor chamber, wherein a portion of the liquid is in the layer;
a thermal interface material (TIM) on the IHS;
a heatsink on the TIM, wherein the TIM is positioned between the IHS and the heatsink;
a bridge in the package substrate, wherein the bridge communicatively couples the die and the package substrate; and
a plurality of solder balls couple the package substrate to a substrate.

7. The semiconductor package of claim 1 , wherein the layer has a uniform thickness.

8. The semiconductor package of claim 6 , wherein the liquid is comprised of water, water-based solutions, ethanol, methanol, or acetone.

9. The semiconductor package of claim 2 , wherein a region of the surface of the layer has a vertical sidewall or a tapered sidewall.

10. A semiconductor package, comprising:
a package substrate on a substrate;
a plurality of dies on the package substrate;
an integrated heat spreader (IHS) over the plurality of dies, the package substrate, and the substrate, wherein the IHS has a lid and a plurality of L-shaped sidewalls, and wherein the IHS has a width that is greater than a width of the package substrate;
a sealant that couples the plurality of L-shaped sidewalls of the IHS to the package substrate; and
a layer below the lid of the IHS, wherein the layer is over the plurality of dies and a top surface of the package substrate, and wherein the layer is on a bottom surface of the lid of the IHS and an interior surface of the plurality of L-shaped sidewalls of the IHS, wherein a vapor chamber is defined by the top surface of the package substrate, the bottom surface of the lid of the IHS, and the interior surface of the plurality of L-shaped sidewalls of the IHS, and wherein the bottom surface of the lid of the IHS is exposed to the vapor chamber.

11. The semiconductor package of claim 10 , wherein the vapor chamber is hermetically sealed with the sealant between the top surface of the package substrate and the plurality of L-shaped sidewalls of the IHS, and wherein the vapor chamber has a vapor space defined by a surface of the layer and the bottom surface of the lid of the IHS.

12. The semiconductor package of claim 11 , wherein the IHS is a low profile IHS, wherein the low profile IHS has a thickness slightly greater than a thickness of the plurality of dies, wherein the layer is over a plurality of surfaces of the plurality of dies, wherein the layer is comprised of one or more wick materials, wherein the one or more wick materials include one or more porous materials, and wherein the one or more porous materials include metals, powders, or graphite.

13. The semiconductor package of claim 12 , wherein the layer thermally couples the plurality of surfaces of the plurality of dies to the bottom surface of the lid of the IHS, wherein the bottom surface of the lid of the IHS faces the top surface of the package substrate and the plurality of surfaces of the plurality of dies, wherein the interior surface of the plurality of L-shaped sidewalls of the IHS faces the plurality of surfaces of the plurality of dies, wherein the plurality of L-shaped sidewalls of the IHS have a first portion and a second portion, wherein the first portion of the plurality of L-shaped sidewalls of the IHS extends horizontally over the top surface of the package substrate and a top surface of the substrate, wherein the second portion of the plurality of L-shaped sidewalls of the IHS extends vertically over the top surface of the substrate, and wherein the first portion of the plurality of L-shaped sidewalls of the IHS has a footprint greater than a footprint of the second portion of the plurality of L-shaped sidewalls of the IHS.

14. The semiconductor package of claim 13 , further comprising:
a hydrophobic layer on the plurality of surfaces of the plurality of dies and the top surface of the package substrate, wherein the hydrophobic layer is between the layer and the plurality of surfaces of the plurality of dies, wherein the hydrophobic layer is between the layer and the top surface of the package substrate, and wherein the hydrophobic layer is between the top surface of the package substrate and an exterior surface of the plurality of L-shaped sidewalls of the IHS;
a liquid in the vapor chamber, wherein a portion of the liquid is in the layer;
a thermal interface material (TIM) on the IHS;
a heatsink on the TIM, wherein the TIM is positioned between the IHS and the heatsink;
a plurality of bridges in the package substrate, wherein the plurality of bridges communicatively couple the plurality of dies to each other; and
a plurality of solder balls couple the package substrate to the substrate.

15. The semiconductor package of claim 11 , wherein the plurality of dies include a first die with a first thickness, and a second die with a second thickness, wherein the first thickness of the first die is different from the second thickness of the second die, and wherein the layer has a substantially uniform thickness or a non-uniform thickness.

16. The semiconductor package of claim 11 , wherein the vapor chamber has a width greater than the width of the package substrate.

17. The semiconductor package of claim 14 , wherein the liquid is comprised of water, water-based solutions, ethanol, methanol, or acetone, and wherein a region of the surface of the layer has a vertical sidewall or a tapered sidewa

Assignees

• Intel Corp

Inventors

• Neal Nicholas
• Haehn Nicholas S
• Chang Je-Young
• Arrington Kyle
• Mccann Aaron
• Cetegen Edvin
• Mahajan Ravindranath V
• Sankman Robert L
• Hackenberg Ken P
• Chan Arguedas Sergio A

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W40/226

  characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461) · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title