Three-dimensional memory device with wiggled drain-select-level isolation structure and methods of manufacturing the same

US11805649B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11805649-B2
Application numberUS-202117385728-A
CountryUS
Kind codeB2
Filing dateJul 26, 2021
Priority dateMar 13, 2019
Publication dateOct 31, 2023
Grant dateOct 31, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; memory openings vertically extending through the alternating stack; memory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel; and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer of the electrically conductive layers and laterally extending generally along a first horizontal direction and having a periodic repetition of lateral wiggles along a second horizontal direction that is perpendicular to the first horizontal direction, wherein the at least one drain-select-level isolation structure cuts through drain-select-level portions of at least some of the memory opening fill structures. 2. The three-dimensional memory device of claim 1 , wherein: the memory opening fill structures comprise multiple rows of memory opening fill structures that are arranged along the first horizontal direction with a first pitch; and the periodic repetition of lateral wiggles has a periodicity of the first pitch along the first horizontal direction. 3. The three-dimensional memory device of claim 2 , wherein: the at least one drain-select-level isolation structure cuts through the drain-select-level portions of the memory opening fill structures in first rows located adjacent to the at least one drain-select-level isolation structure; and the at least one drain-select-level isolation structure does not cut through the drain-select-level portions of the memory opening fill structures in second rows that are spaced from the at least one drain-select-level isolation structure by the first row of memory opening fill structures. 4. The three-dimensional memory device of claim 3 , wherein: the drain-select-level portions of the memory opening fill structures located in the first rows have a horizontal cross-sectional shape of a segment of a circle having two planar sidewalls corresponding to two chords extending between end points of a major arc; and the drain-select-level portions of the memory opening fill structures located in the second rows have a horizontal cross-sectional shape of a circle. 5. The three-dimensional memory device of claim 3 , wherein: the memory opening fill structures located in the first rows comprise a stepped sidewall including a first sidewall segment underlying a horizontal plane including each bottom surface of the at least one drain-select-level isolation structure, a second sidewall segment overlying the horizontal plane, and a connecting segment that connects the first sidewall segment to the second sidewall segment within the horizontal plane; and the at least one drain-select-level isolation structure does not contact, and is laterally spaced from, the memory opening fill structures located in the second rows. 6. The three-dimensional memory device of claim 1 , wherein the at least one drain-select-level isolation structure comprises: a vertically-extending dielectric material portion located between the adjacent first rows of the memory opening fill structures; and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer. 7. A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; memory openings vertically extending through the alternating stack; memory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel; and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer of the electrically conductive layers, wherein the at least one drain-select-level isolation structure comprises a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer. 8. The three-dimensional memory device of claim 7 , wherein: the vertically-extending dielectric material portion has a lateral extent that is bounded by a pair of vertical planes that generally extend along a first horizontal direction and located between a neighboring pair of rows of the memory opening fill structures; and the laterally-protruding dielectric material portions laterally protrude along a second horizontal direction that is perpendicular to the first horizontal direction from a respective one of the pair of vertical planes. 9. The three-dimensional memory device of claim 7 , wherein: the at least one drain-select-level isolation structure cuts through drain-select-level portions of at least some of the memory opening fill structures; and the memory opening fill structures comprise multiple rows of memory opening fill structures that are arranged along the first horizontal direction with a first pitch. 10. The three-dimensional memory device of claim 9 , wherein: the at least one drain-select-level isolation structure cuts through the drain-select-level portions of the memory opening fill structures in first rows located adjacent to the at least one drain-select-level isolation structures; and the at least one drain-select-level isolation structure does not cut through the drain-select-level portions of the memory opening fill structures in second rows that are spaced from the at least one drain-select-level isolation structure by the first row of memory opening fill structures. 11. The three-dimensional memory device of claim 10 , wherein the at least one drain-select-level isolation structure comprises a periodic repetition of lateral wiggles along the second horizontal direction, and the periodic repetition of lateral wiggles has a periodicity of the first pitch along the first horizontal direction. 12. The three-dimensional memory device of claim 11 , wherein: the drain-select-level portions of the memory opening fill structures located in the first rows have a horizontal cross-sectional shape of a segment of a circle having two planar sidewalls corresponding to two chords extending between end points of a major arc; and the drain-select-level portions of the memory opening fill structures located in the second rows have a horizontal cross-sectional shape of a circle. 13. The three-dimensional memory device of claim 10 , wherein the pair of lengthwise sidewalls of the vertically-extending dielectric material portion comprises a pair of straight lengthwise sidewall segments that are parallel to the first horizontal direction. 14. The three-dimensional memory device of claim 10 , wherein: the memory opening fill structures located in the first rows comprise a stepped sidewall including a first sidewall segment underlying a horizontal plane including each bottom surface of the at least one drain-select-level isolation structure, a second sidewall segment overlying the horizontal plane, and a connecting segment that connects the first sidewall segment to the second sidewall segment within the horizontal plane; and the at least one drain-select-level isolation structure does not contact, and is laterally

Assignees

Inventors

Classifications

  • for Group V materials or Group III-V materials · CPC title

  • by liquid etching only · CPC title

  • using masks for insulating materials · CPC title

  • formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

  • using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

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What does patent US11805649B2 cover?
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a …
Who is the assignee on this patent?
Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification H10B43/27. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 31 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).