Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof

Patent metadata

Field	Value
Publication number	US-9972640-B1
Application number	US-201615354067-A
Country	US
Kind code	B1
Filing date	Nov 17, 2016
Priority date	Nov 17, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film;
drain select level channel portions overlying a respective memory level channel portion, wherein a geometrical center of each drain select level channel portion is laterally offset with respect to a geometrical center of the respective memory level channel portion;
drain select level gate dielectrics laterally surrounding and contacting a respective subset of the drain select level channel portions; and
drain select level gate electrodes laterally surrounding respective drain select level gate dielectrics;
wherein:
the memory stack structures are arranged as a two-dimensional periodic array including respective rows that extend along a first horizontal direction and have a uniform inter-row pitch along a second horizontal direction;
the drain select level channel portions are arranged in respective rows that extend along the first horizontal direction and have a periodically modulated inter-row center-to-center spacing having a periodicity of twice the inter-row pitch of the two-dimensional periodic array of the memory stack structures;
the drain select level channel portions are arranged as pairs of rows that extend along the first horizontal direction;
two rows within each pair of rows has a first inter-row center-to-center spacing that is less than the inter-row pitch of the two-dimensional periodic array of the memory stack structures;
adjacent rows that belong to two different neighboring pairs of rows have a second inter-row center-to-center spacing that is greater than the inter-row pitch of the two-dimensional periodic array of the memory stack structures, and greater than the first inter-row center-to-center spacing;
the drain select level gate electrode has a continuous set of sidewalls that laterally surrounds a respective pair of rows of drain select level channel portions;
the drain select level gate electrodes are physically adjoined in each pair of rows, but are physically disjoined among one another between each pair of rows;
each drain select level channel portion within the pair of rows of the drain select level channel portions is laterally surrounded by a respective one of the drain select level gate electrodes;
the continuous set of sidewalls of the drain select level gate electrode comprises convex outer sidewalls that partially laterally surround the respective drain select level channel portion in the pair of rows, and planar, non-convex outer sidewalls that surround an elongated template structure; and
the electrically conductive layers have planar, non-convex outer sidewalls.

2. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or replaced with, electrically conductive layers;
forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film;
forming drain select level channel portions over the memory level channel portions after the step of forming the memory stack structures,
forming drain select level gate dielectrics on and around the drain select level channel portions; and
forming drain select level gate electrodes around the drain select level gate dielectrics;
wherein:
a geometrical center of each drain select level channel portion is laterally offset with respect to a geometrical center of a respective underlying memory level channel portion;
the memory stack structures are formed as a two-dimensional periodic array including respective rows that extend along a first horizontal direction and have a uniform inter-row pitch along a second horizontal direction;
the drain select level channel portions are arranged in respective rows that extend along the first horizontal direction and have a periodically modulated inter-row center-to-center spacing having a periodicity of twice the inter-row pitch of the two-dimensional periodic array of the memory stack structures;
the drain select level channel portions are arranged as pairs of rows that extend along the first horizontal direction;
two rows within each pair of rows has a first inter-row center-to-center spacing that is less than the inter-row pitch of the two-dimensional periodic array of the memory stack structures; and
adjacent rows that belong to two different neighboring pairs of rows have a second inter-row center-to-center spacing that is greater than the inter-row pitch of the two-dimensional periodic array of the memory stack structures, and greater than the first inter-row center-to-center spacing;
further comprising:
forming a stack of a drain select level gate dielectric layer and a drain select level gate electrode layer over the drain select channel portions; and
removing horizontal portions of the stack of the drain select level gate dielectric layer and the drain select level gate electrode layer, wherein remaining portions of the drain select level gate dielectric layer constitute the drain select level gate dielectrics and remaining portions of the drain select level gate electrode layer constitute the drain select level gate electrodes;
wherein:
the drain select level gate electrode has a continuous set of sidewalls that laterally surround a respective pair of rows of drain select level channel portions;
the drain select level gate electrodes are physically adjoined in each pair of rows, but are physically disjoined among one another between each pair of rows;
the continuous set of sidewalls of the drain select level gate electrode comprises convex outer sidewalls that that partially laterally surround the respective drain select level channel portion in the pair of rows and planar, non-convex outer sidewalls that surround an elongated template structure;
the electrically conductive layers have planar, non-convex outer sidewalls;
the drain select level gate dielectrics are physically disjoined among one another between each pair of rows; and
each drain select level gate dielectric laterally surrounds, and contacts, a respective subset of the drain select level channel portions that are arranged as the pair of rows that laterally extend along a first horizontal direction.

3. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film;
drain select level channel portions overlying a respective memory level channel portion;
drain select level gate dielectrics laterally surrounding and contacting a respective subset of the drain select level channel portions; and
drain select level gate electrodes laterally surrounding respective drain select level gate dielectrics, wherein the drain select level gate electrodes comprise convex outer sidewalls;

wherein:
the memory stack structures are arranged as a two-dimensional periodic array including respective rows that extend along a first horizontal direction and have a uniform inter-row pitch along a second horizontal direction;
the drain select level channel portions are arranged in respective rows that extend along the first horizontal direction and have a periodically mod

Assignees

• Sandisk Technologies Llc

Inventors

• Kai James
• Chowdhury Murshed
• Liu Jin
• Alsmeier Johann

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title