Three-dimensional memory device with aluminum-containing etch stop layer for backside contact structure and method of making thereof

Patent metadata

Field	Value
Publication number	US-9728547-B1
Application number	US-201615159034-A
Country	US
Kind code	B1
Filing date	May 19, 2016
Priority date	May 19, 2016
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Unwanted erosion of dielectric materials around a backside contact trench can be avoided or minimized employing an aluminum oxide liner. An aluminum oxide liner can be formed inside an insulating material layer in a backside contact trench to prevent collateral etching of the insulating material at an upper portion of the backside contact trench during an anisotropic etch that forms an insulating spacer. Alternatively, an aluminum oxide layer can be employed as a backside blocking dielectric layer. An upper portion of the aluminum oxide layer can be converted into an aluminum compound layer including aluminum and a non-metallic element other than oxygen at an upper portion of the trench, and can be employed as a protective layer during formation of a backside contact structure.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a trench extending through the alternating stack;
an aluminum oxide backside blocking dielectric layer including liner portions located between the electrically conductive layers and the insulating layers and a vertical portion located at a periphery of the trench;
an annular aluminum compound portion located at an upper portion of the trench and comprising aluminum and a non-metallic element other than oxygen; and
a contact via structure located inside the vertical portion of the aluminum oxide backside blocking dielectric layer and the annular aluminum compound portion and contacting a portion of the substrate.

2. The three-dimensional memory device of claim 1 , wherein the annular aluminum compound portion comprises a material selected from aluminum silicon oxide, aluminum nitride, aluminum oxynitride, aluminum oxyfluoride and aluminum fluoride.

3. The three-dimensional memory device of claim 1 , wherein a composition of the annular aluminum compound portion differs from a composition of the aluminum oxide backside blocking dielectric layer by a presence of the non-metallic element other than oxygen therein.

4. The three-dimensional memory device of claim 1 , further comprising a horizontal aluminum compound portion having a same composition as the annular aluminum compound portion and overlying the alternating stack.

5. The three-dimensional memory device of claim 4 , further comprising at least one contact via structure extending to the electrically conductive layers and having a topmost surface within a same horizontal plane as a top surface of the horizontal aluminum compound portion.

6. The three-dimensional memory device of claim 1 , wherein a bottom surface of the annular aluminum compound portion contacts a top surface of the aluminum oxide backside blocking dielectric layer.

7. The three-dimensional memory device of claim 1 , further comprising an insulating spacer laterally surrounding the contact via structure, and laterally surrounded by the vertical portion of the aluminum oxide backside blocking dielectric layer and the annular aluminum compound portion.

8. The three-dimensional memory device of claim 7 , wherein the insulating spacer comprises a material selected from silicon oxide and silicon nitride.

9. The three-dimensional memory device of claim 1 , wherein the portion of the substrate that contacts the contact via structure comprises a source region.

10. The three-dimensional memory device of claim 1 , further comprising a plurality of memory stack structures extending through the alternating stack, wherein each of the plurality of memory stack structures comprises a memory film and a semiconductor channel that is laterally surrounded by the memory film.

11. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Assignees

• Sandisk Technologies Llc

Inventors

• Ohsaki Shingo
• Kariya Hiroshi
• Maede Takuro
• Kawamura Takeshi

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6302

  Non-deposition formation processes · CPC title