On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

Patent metadata

Field	Value
Publication number	US-10236300-B2
Application number	US-201715784549-A
Country	US
Kind code	B2
Filing date	Oct 16, 2017
Priority date	Jul 25, 2017
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory stack structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and spaced apart along a second horizontal direction, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film;
an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures along the first horizontal direction and the second horizontal direction;
drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies; and
a first drain select level isolation strip comprising a dielectric material located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls, wherein each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.

2. The three-dimensional memory device of claim 1 , wherein each of the drain select level assemblies comprises a drain select level channel portion contacting a respective memory level channel portion and a gate dielectric laterally surrounding the drain select level channel portion.

3. The three-dimensional memory device of claim 2 , wherein:
each of the gate dielectrics has a cylindrical configuration;
top surfaces of the drain select gate electrodes are adjoined to a respective subset of outer sidewalls of the gate dielectrics; and
each of the convex sidewall portions is equidistant from a sidewall of a respective most proximal one of the drain select level assemblies.

4. The three-dimensional memory device of claim 2 , wherein each of the drain select level assemblies comprises a drain region contacting top surfaces of the drain select level channel portion.

5. The three-dimensional memory device of claim 4 , wherein a peripheral portion of the drain region protrudes outward from an outer sidewall of the gate dielectric and overhangs the gate dielectric.

6. The three-dimensional memory device of claim 4 , wherein:
the memory film comprises a stack, from outside to inside, of a blocking dielectric, charge storage elements, and a tunneling dielectric; and
the gate dielectric comprises a material that is different from a material of the charge storage elements.

7. The three-dimensional memory device of claim 4 , further comprising a dielectric fill material layer contacting, and laterally surrounding, each of the drain regions, and contacting top surfaces of the drain select gate electrodes.

8. The three-dimensional memory device of claim 7 , further comprising a second drain select level isolation strip, wherein:
each of the pair of lengthwise sidewalls of the first drain select level isolation strip contacts a respective one of the drain select gate electrodes;
the second drain select level isolation strip comprises a first lengthwise sidewall and a second lengthwise sidewall;
the first lengthwise sidewall contacts a respective one of the drain select gate electrodes; and
an entirety of the second lengthwise sidewall contacts a sidewall of a portion of the dielectric fill material layer.

9. The three-dimensional memory device of claim 7 , wherein each respective drain select level assembly is laterally surrounded by only one drain select gate electrode.

10. The three-dimensional memory device of claim 7 , wherein an insulating spacer strip is located between a first horizontal drain select gate electrode and a second horizontal drain select gate electrode which is electrically connected to the first horizontal drain select gate electrode by a vertically extending portion.

11. The three-dimensional memory device of claim 7 , wherein each of the gate dielectrics contacts, and is laterally encircled by, a respective one of the vertically extending portions of the drain select gate electrodes.

12. The three-dimensional memory device of claim 1 , wherein each drain select level channel portion contacts a top surface of a respective enhanced doping region that contacts a respective vertical semiconductor channel.

13. The three-dimensional memory device of claim 1 , wherein each laterally alternating sequence of planar sidewall portions and convex sidewall portions vertically extend from a bottom surface of the first drain select level isolation strip to a top surface of the first drain select level isolation strip.

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Tsutsumi Masanori
• Yada Shinsuke
• Nagamine Sayako
• Alsmeier Johann

Classifications

• H01L27/11529

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic