Semiconductor package including semiconductor chips

Patent metadata

Field	Value
Publication number	US-11791303-B2
Application number	US-202318099092-A
Country	US
Kind code	B2
Filing date	Jan 19, 2023
Priority date	Oct 26, 2020
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate;
a semiconductor chip on the package substrate;
a plurality of first conductive connections connecting the semiconductor chip to the package substrate;
a first spacer and a second spacer on the package substrate, each of the first spacer and the second spacer horizontally spaced apart from the semiconductor chip;
a first tower and a second tower each including a plurality of memory chips, a first memory chip disposed at a lowermost end of the first tower and vertically overlapping the semiconductor chip and the first spacer from a top-down view, and a second memory chip disposed at a lowermost end of the second tower and vertically overlapping the semiconductor chip and the second spacer from a top-down view; and
a plurality of first adhesive layers including an adhesive layer covering a lower surface of the first memory chip and partially covering an upper surface of the semiconductor chip and an adhesive layer covering a lower surface of the second memory chip and partially covering the upper surface of the semiconductor chip.

2. The semiconductor package of claim 1 , wherein:
the plurality of first conductive connections partially pass through the plurality of first adhesive layers.

3. The semiconductor package of claim 1 , further comprising:
a plurality of dummy chips on the first tower and the second tower.

4. The semiconductor package of claim 1 , wherein:
the first spacer and the second spacer are dummy chips.

5. The semiconductor package of claim 1 , wherein:
the semiconductor chip is a first semiconductor chip, the first spacer is a second semiconductor chip and the second spacer is a third semiconductor chip, wherein each one of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip is disposed below at least one of the first tower and the second tower.

6. A semiconductor package comprising:
a package substrate including a plurality of substrate pads;
a semiconductor chip on the package substrate and including a plurality of pads;
a plurality of first conductive connections connecting the semiconductor chip to the package substrate;
a plurality of towers apart from one another, each including a plurality of memory chips, a lowermost memory chip of each of the plurality of towers overlapping the semiconductor chip from a top-down view; and
a plurality of adhesive layers attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip,
wherein at least one of the plurality of pads are connected to one of the plurality of memory chips and at least one of the plurality of pads are connected to the package substrate.

7. The semiconductor package of claim 6 , wherein:
the plurality of pads includes a plurality of first pads arranged in two columns along a first direction, and
the plurality of first pads is connected to the plurality of memory chips.

8. The semiconductor package of claim 7 , wherein:
the plurality of pads further includes a plurality of second pads arranged in two rows along a second direction crossing the first direction, and
the plurality of first pads is connected to the package substrate.

9. The semiconductor package of claim 6 , wherein:
an interval between the lowermost memory chips of each of the plurality of towers is greater than 0.1 mm.

10. The semiconductor package of claim 6 , wherein:
the lowermost memory chip of each of the plurality of towers overlaps an upper portion of at least one of the plurality of pads, from a top-down view.

11. The semiconductor package of claim 6 , further comprising:
a plurality of second conductive connections connecting the plurality of towers to the package substrate and the semiconductor chip, and
wherein the plurality of second conductive connections includes a set of second conductive connections in contact with at least one of the plurality of pads.

12. The semiconductor package of claim 6 , wherein:
the semiconductor chip is a first semiconductor chip, and the semiconductor package further comprises a second semiconductor chip and a third semiconductor chip and the first semiconductor chip is between the second semiconductor chip and the third semiconductor chip, and
the second semiconductor chip and the third semiconductor chip include a plurality of pads connected to one of the plurality of memory chips.

13. The semiconductor package of claim 6 , wherein:
the semiconductor chip is a first semiconductor chip, and the semiconductor package further comprises a second semiconductor chip and a third semiconductor chip and the first semiconductor chip is between the second semiconductor chip and the third semiconductor chip, and
at least one of a plurality of pads of the second semiconductor chip and at least one of a plurality of pads of the third semiconductor chip are connected to the one of the plurality of substrate pads through the plurality of first conductive connections.

14. A semiconductor package comprising:
a package substrate including a plurality of substrate pads;
a semiconductor chip on the package substrate and including a plurality of pads;
a plurality of conductive connections connecting the semiconductor chip to the package substrate;
a first tower and a second tower each including a plurality of memory chips, a lowermost memory chip of each of the first and second towers overlapping the semiconductor chip from a top-down view; and
a plurality of adhesive layers respectively attached between the lowermost memory chip of the first and second towers and the semiconductor chip,
wherein the plurality of pads includes a plurality of first pads connected to the first tower and a plurality of second pads connected to the second tower, and
wherein at least one of the plurality of first pads are disposed adjacent to at least one of the plurality of second pads.

15. The semiconductor package of claim 14 , wherein:
the plurality of first pads and the plurality of second pads are alternately arranged.

16. The semiconductor package of claim 14 , wherein:
the plurality of pads includes a plurality of third pads connected to the plurality of substrate pads through the plurality of conductive connections.

17. The semiconductor package of claim 14 , wherein:
an interval between the lowermost memory chips of each of the first tower and the second tower is greater than 0.1 mm.

18. The semiconductor package of claim 14 , wherein:
the lowermost memory chip of each of the first tower and the second tower overlaps an upper portion of at least one of the plurality of pads, from a top-down view.

19. The semiconductor package of claim 14 , wherein:
the semiconductor chip is a first semiconductor chip, the semiconductor package further comprises a second semiconductor chip and a third semiconductor chip, and the first semiconductor chip is between the second semiconductor chip and the third semiconductor chip, and
the second semiconductor chip and the third semiconductor chip include a plurality of pads connected to one of the plurality of memory chips.

20. The semiconductor package of claim 14 , wherein:
the semiconductor chip is a first semiconductor chip, the semiconductor package further comprises a second semiconductor chip and a third semiconductor chip, and the first semiconductor chip is between the second semiconductor chip and the third semiconductor chip, and
at least one of the plurality of pads of the second semicondu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Hyungu
• Sung Jaekyu

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title