Semiconductor structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-11756795-B2
Application number	US-202017035591-A
Country	US
Kind code	B2
Filing date	Sep 28, 2020
Priority date	Dec 23, 2019
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

The present disclosure provides a method for forming a semiconductor structure. The method includes providing a target etching layer; sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer; performing a first etching process on the anti-reflection layer to remove a surface portion of the anti-reflection layer using the patterned structure as a mask; performing a surface treatment process on the patterned structure; and performing a second etching process on the anti-reflection layer until exposing a surface of the initial mask layer.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a target etching layer;
sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer;
prior to performing a plasma treatment process on the patterned structure, performing, using the patterned structure as a mask, a first etching process on the anti-reflection layer to remove only surface portions of the anti-reflection layer to form recesses in the anti-reflection layer exposed by the patterned structure, wherein unexposed portions of the anti-reflection layer provide a fixed pitch under the patterned structure;
performing the plasma treatment process on the recessed anti-reflection layer and on the patterned structure to provide the patterned structure with an improved line width roughness;
after the plasma treatment process performed on the patterned structure, performing a second etching process on the anti-reflection layer through the recesses in the anti-reflection layer, until exposing a surface of the initial mask layer; and
etching, using the patterned structure with the improved line width roughness and the unexposed portions of the anti-reflection layer with the fixed pitch as an etch mask, the initial mask layer to form a patterned mask layer.

2. The method according to claim 1 , wherein:
a processing gas used in the plasma treatment process includes HBr, H 2 , Ar, or a combination thereof.

3. The method according to claim 2 , wherein:
the processing gas includes HBr; and
processing parameters used in the plasma treatment process include:
a flow rate of HBr in a range of approximately 30 sccm to 500 sccm;
a pressure in a range of approximately 3 mTorr to 100 mTorr; and
a power in a range of approximately 50 W to 1000 W.

4. The method according to claim 1 , wherein:
a thickness of the surface portion of the anti-reflection layer removed by the first etching process accounts for approximately 5% to 50% of a thickness of an entirety of the anti-reflection layer.

5. The method according to claim 1 , wherein:
each of the first etching process and the second etching process includes a dry etching process.

6. The method according to claim 5 , wherein:
processing parameters used in the first etching process and the second etching process are same, wherein the processing parameters of the first etching process and the second etching process include:
an etching gas including one or more of CH X F Y gases, where x and y are both natural numbers, x+y=4, and x=0, 1, 2, 3;
an etching pressure in a range of approximately 5 mTorr to 100 mTorr; and
an etching power in a range of approximately 100 W to 1200 W.

7. The method according to claim 1 , wherein:
the target etching layer is made of a low-K dielectric material or an ultra-low-K dielectric material, including SiOH, SiCOH, fluorosilicate glass (FSG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), hydrogenated silsesquioxane (HSQ, (HSiO 1.5 ) n ), or methylsilsesquioxane (MSQ, (CH 3 SiO 1.5 ) n ).

8. The method according to claim 1 , wherein:
the target etching layer is made of a dielectric material, including silicon oxide (SiO x ), silicon nitride (SiN x ), or a conductive material, including titanium nitride (TiN x ).

9. The method according to claim 1 , wherein:
the anti-reflection layer is made of an inorganic anti-reflection material, including silica, carbon-doped silica, nitrogen-doped silica, or a combination thereof.

10. The method according to claim 1 , wherein:
the anti-reflection layer is made of an organic anti-reflection material, including an unmodified organic anti-reflection material, or an organic anti-reflection material containing silicon or modified elements other than silicon.

11. The method according to claim 1 , wherein:
prior to performing the plasma treatment process on the patterned structure, a roughness of the patterned structure is a first roughness; and
after performing the plasma treatment process on the patterned structure, the roughness of the patterned structure is a second roughness, wherein:
the second roughness is less than the first roughness.

12. The method according to claim 1 , wherein:
etching the initial mask layer using the patterned structure and the anti-reflection layer as the etch mask includes a dry etching process, wherein processing parameters used in the dry etching process include:
an etching gas including sulfur dioxide and oxygen, or sulfur dioxide and nitrogen;
a flow rate of the etching gas is in a range of approximately 10 sccm to 500 sccm;
an etching pressure in a range of approximately 10 mTorr to 50 mTorr; and
an etching power in a range of approximately 100 W to 1200 W.

13. The method according to claim 1 , further including:
etching the target etching layer using the patterned mask layer as an etch mask to form a target pattern layer without removing the unexposed portions of the anti-reflection layer with the fixed pitch.

14. The method according to claim 13 , wherein:
the target etching layer is made of silicon oxide (SiO x ) or silicon nitride (SiN x ); and
etching the target etching layer includes a dry etching process, wherein processing parameters used in the dry etching process include:
an etching gas including one or more of CH X F Y gases, where x and y are both natural numbers, x+y=4, and x=0, 1, 2, 3;
an etching pressure in a range of approximately 5 mTorr to 100 mTorr; and
an etching power in a range of approximately 100 W to 1200 W.

15. A semiconductor structure formed by the method according to claim 1 .

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Ji Shiliang
• Liu Panpan
• Zhang Haiyang

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/2043 Primary

  using an anti-reflective coating · CPC title

• H10P76/204 Primary

  of organic photoresist masks · CPC title

• H10P50/287

  by chemical means · CPC title