Method of forming patterns and method of manufacturing a semiconductor device using the same

Patent metadata

Field	Value
Publication number	US-9905754-B1
Application number	US-201715630046-A
Country	US
Kind code	B1
Filing date	Jun 22, 2017
Priority date	Jan 11, 2017
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

In a method of forming a pattern of a semiconductor device, a first mask layer and an anti-reflective coating layer may be sequentially formed on a substrate. A photoresist layer may be formed on the anti-reflective coating layer. The photoresist layer may be exposed and developed to form a first preliminary photoresist pattern. A first ion beam etching process may be performed on the first preliminary photoresist pattern to form a second preliminary photoresist pattern. A second ion beam etching process may be performed on the second preliminary photoresist pattern to form a photoresist pattern. A second incident angle of an ion beam in the second ion beam etching process may be greater than a first incident angle of an ion beam in the first ion beam etching process. The anti-reflective coating layer and the first mask layer may be etched using the photoresist pattern as an etching mask to form a mask structure.

First claim

What is claimed is:

1. A method of forming a pattern of a semiconductor device, comprising:
sequentially forming a first mask layer and an anti-reflective coating layer on a substrate;
forming a photoresist layer on the anti-reflective coating layer;
exposing and developing the photoresist layer to form a first preliminary photoresist pattern;
performing a first ion beam etching process on the first preliminary photoresist pattern to form a second preliminary photoresist pattern, wherein an ion beam in the first ion beam etching process is incident on an upper surface of the substrate at a first incident angle;
performing a second ion beam etching process on the second preliminary photoresist pattern to form a photoresist pattern, wherein an ion beam in the second ion beam etching process is incident on the upper surface of the substrate at a second incident angle greater than the first incident angle; and
etching the anti-reflective coating layer and the first mask layer using the photoresist pattern as an etching mask to form a mask structure.

2. The method of claim 1 , wherein a sidewall of the first preliminary photoresist pattern is partially etched during the first ion beam etching process, so that a sidewall of the second preliminary photoresist pattern has a roughness property different from a roughness property of the sidewall of the first preliminary photoresist pattern.

3. The method of claim 1 , wherein a surface of the anti-reflective coating layer is partially etched, and elements of the etched anti-reflective coating layer are re-deposited on a sidewall of the second preliminary photoresist pattern, during the second ion beam etching process.

4. The method of claim 1 , wherein the first and second ion beam etching processes are performed using a voltage in a range of from about 50V to about 500V.

5. The method of claim 1 , wherein the first and second ion beam etching processes are performed using an inert gas including argon (Ar), xenon (Xe) or neon (Ne).

6. The method of claim 1 , wherein the first incident angle is in a range of from about 20 degrees to about 50 degrees.

7. The method of claim 1 , wherein the second incident angle is in a range of from about 70 degrees to about 90 degrees.

8. The method of claim 1 , further comprising:
forming an etch target layer between the substrate and the first mask layer prior to sequentially faulting the first mask layer and the anti-reflective coating layer on the substrate; and
after forming the mask structure, etching the etch target layer using the mask structure as an etching mask to form a pattern structure.

9. The method of claim 1 , further comprising, after forming the mask structure:
performing a third ion beam etching process on the mask structure to form a first mask structure, wherein an ion beam in the third ion beam etching process is incident on the upper surface of the substrate at a third incident angle; and
performing a fourth ion beam etching process on the first mask structure to form a second mask structure, wherein an ion beam in the fourth ion beam etching process is incident on the upper surface of the substrate at a fourth incident angle greater than the third incident angle.

10. The method of claim 1 , further comprising, after forming the mask structure:
forming a second mask layer to fill a gap included in the mask structure; and
planarizing the second mask layer until an upper surface of the mask structure is exposed to form a second mask.

11. The method of claim 10 , further comprising:
forming an etch target layer between the substrate and the first mask layer prior to sequentially forming the first mask layer and the anti-reflective coating layer on the substrate; and
after forming the second mask, etching the etch target layer using the second mask as an etching mask to form a pattern structure.

12. A method of forming a pattern of a semiconductor device, comprising:
sequentially forming an etch target layer and a first mask layer on a substrate;
forming a first photoresist pattern on the first mask layer;
etching the first mask layer using the first photoresist pattern as an etching mask to form a first preliminary mask pattern;
performing a first ion beam etching process on the first preliminary mask pattern to form a second preliminary mask pattern, wherein an ion beam in the first ion beam etching process is incident on an upper surface of the substrate at a first incident angle;
performing a second ion beam etching process on the second preliminary mask pattern to form a first mask, wherein an ion beam in the second ion beam etching process is incident on the upper surface of the substrate at a second incident angle greater than the first incident angle; and
etching the etch target layer using the first mask as an etching mask to form a pattern structure.

13. The method of claim 12 , wherein a sidewall of the first preliminary mask pattern is partially etched during the first ion beam etching process, so that a sidewall of the second preliminary mask pattern has a roughness property different from a roughness property of the sidewall of the first preliminary mask pattern.

14. The method of claim 12 , wherein a surface of the etch target layer is partially etched, and elements of the etched etch target layer are re-deposited on a sidewall of the second preliminary mask pattern, during the second ion beam etching process.

15. The method of claim 12 , wherein the first and second ion beam etching processes are performed using an inert gas including argon (Ar), xenon (Xe) or neon (Ne).

16. A method of manufacturing a semiconductor device, comprising:
forming an etch target layer including a magnetic tunnel junction layer on a substrate;
sequentially forming a first mask layer and an anti-reflective coating layer on the etch target layer;
forming a first preliminary photoresist pattern on the anti-reflective coating layer, the first preliminary photoresist pattern including a plurality of contact holes;
performing a first ion beam etching process, using an ion beam incident at a first incident angle less than ninety degrees with an upper surface of the substrate, on the first preliminary photoresist pattern to form a second preliminary photoresist pattern, wherein the ion beam etching process smoothes sidewalls of contact holes; and
performing a second ion beam etching process, using an ion beam incident at a second incident angle greater than the first incident angle, on the second preliminary photoresist pattern to form a photoresist pattern.

17. The method of claim 16 , further comprising; performing a third ion beam etching process on the photoresist pattern, wherein an ion beam in the third ion beam etching process is incident on the upper surface of the substrate at a third incident angle.

18. The method of claim 16 , further comprising: etching the anti-reflective coating layer and the first mask layer using the photoresist pattern as an etching mask to form a mask structure.

19. The method of claim 18 , further comprising:
forming a hard mask having a pillar shape to fill the contact holes in the mask structure.

20. The method of claim 19 , further comprising:
etching the etch target layer using a hard mask to form a mask structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Hye Ji
• Kong Yoo Chul
• Kim Jong Kyu
• Kim Sang Kuk
• Lee Yil Hyung

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P50/268

  of silicon-containing layers · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/283

  by chemical means · CPC title