Directional processing to remove a layer or a material formed over a substrate

Patent metadata

Field	Value
Publication number	US-10354874-B2
Application number	US-201715812750-A
Country	US
Kind code	B2
Filing date	Nov 14, 2017
Priority date	Nov 14, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device over a substrate having a multi-layer resist over a hard mask layer, the method comprising:
etching the multi-layer resist to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer; and
directionally providing ions at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer,
wherein the multi-layer resist comprises a bottom layer, a middle layer formed over the bottom layer, and a top photoresist layer formed over the middle layer and wherein the middle layer and the hard mask layer have a similar etch selectivity to an etch chemistry of the directional etch process.

2. The method of claim 1 , wherein the plurality of openings provide a shadowing effect to limit the ions directionally provided from contacting the hard mask layer.

3. The method of claim 1 , wherein the ions are directionally provided by an directional etch process.

4. The method of claim 1 , further comprising:
patterning the top photoresist layer to form a top photoresist layer mask; and
etching the middle layer through the top photoresist layer mask to form a middle layer mask.

5. The method of claim 4 ,
wherein the etching the multi-layer resist to form the plurality of openings in the multi-layer resist comprises etching the bottom layer through the middle layer mask to form a plurality of openings in the bottom layer; and
wherein the directional etch process removes the middle layer mask.

6. The method of claim 5 , wherein the directional etch process comprises directing etch ions to predominately contact sidewalls of the middle layer and the bottom layer rather than the hard mask layer.

7. The method of claim 1 , wherein the ions are directionally provided by an directional implant process.

8. The method of claim 7 , wherein the etching the multi-layer resist to form the plurality of openings in the multi-layer resist comprises etching a bottom layer through a middle layer mask to form a plurality of openings in the bottom layer; and
wherein the directional implant process comprises directing implant ions to predominately contact sidewalls of the middle layer mask rather than bottom layer and rather than the hard mask layer.

9. The method of claim 7 , wherein the etching the multi-layer resist to form the plurality of openings in the multi-layer resist comprises etching a bottom layer through a middle layer mask to form a plurality of openings in the bottom layer; and
wherein the directional implant process softens the middle layer mask.

10. The method of claim 9 , further comprising etching the multi-layer resist by softening the middle layer mask prior to removing the middle layer mask from the multi-layer resist.

11. A method of manufacturing a semiconductor device, the method comprising:
forming a hard mask layer over a substrate;
forming a bottom layer over the hard mask layer;
forming a middle layer over the bottom layer;
forming a photo resist pattern over the middle layer;
patterning the middle layer by using the photo resist pattern as an etching mask;
removing the photo resist pattern from the patterned middle layer;
patterning the bottom layer by using the patterned middle layer based on the photo resist pattern as another etching mask; and
selectively etching the patterned middle layer with respect to the hard mask layer by using a directional etching process.

12. The method of claim 11 , wherein the middle layer is made of a first silicon containing material and the hared mask layer is made of a second silicon containing material.

13. The method of claim 11 , further comprising softening the patterned middle layer prior to removing the patterned middle layer.

14. The method of claim 11 , wherein:
the direction etching process employs a plasma etching process, and
etch ions generated by plasma are supplied to the patterned middle layer with an angle α with respect to a normal direction of the substrate, such that the etch ions do not cause damage to the hard mask layer.

15. The method of claim 14 , wherein the angle α is adjusted based on an aspect ratio of the patterned middle layer and the patterned bottom layer.

16. The method of claim 14 , wherein the angle α is in a range from 5 degrees to 30 degrees.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a hard mask layer over a substrate;
forming a bottom layer over the hard mask layer;
forming a middle layer over the bottom layer;
forming a photo resist pattern over the middle layer;
patterning the middle layer by using the photo resist pattern as an etching mask;
removing the photo resist pattern from the patterned middle layer;
patterning the bottom layer by using the patterned middle layer based on the photo resist pattern as another etching mask;
selectively implanting ions to the patterned middle layer with respect to the hard mask layer by using a directional ion implantation process; and
removing the patterned middle layer.

18. The method of claim 17 , wherein:
implantation ions are supplied to the patterned middle layer with angles ±α with respect to a normal direction of the substrate, such that the implantation ions do not reach the hard mask layer.

19. The method of claim 18 , wherein a is in a range from 5 degrees to 30 degrees.

20. The method of claim 18 , wherein the implantation ions include carbon, and the removing the patterned middle layer includes causing carbons in the middle layer to be converted to carbon dioxide.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Shih-Chun
• Lin Chin-Hsiang
• Lai Chien-Wen
• Liu Ru-Gun
• Lin Wei-Liang
• Chang Ya Hui
• Yen Yung-Sung
• Shen Yu-Tien
• Yeh Ya-Wen

Classifications

• H10P95/066

  the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/033

  in openings in dielectrics · CPC title