Hybrid under-bump metallization component

Patent metadata

Field	Value
Publication number	US-11749605-B2
Application number	US-202017116488-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	Sep 20, 2018
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

First claim

What is claimed is:

1. A device, comprising:
an under-bump metallization component comprising a superconducting interconnect component and a solder wetting component; and
a solder bump coupled to the superconducting interconnect component and the solder wetting component;
one or more solder diffusion layers disposed on a plurality of portions of a superconducting layer; and
a channel between the one or more solder diffusion layers and the plurality of portions of the superconducting layer, wherein the solder is in direct contact with the plurality of portions of the superconducting layer.

2. The device of claim 1 , wherein the solder wetting component encloses the superconducting interconnect component.

3. The device of claim 1 , wherein the solder wetting component comprises material that reacts with solder to form an intermetallic compound layer, thereby facilitating improved mechanical coupling of the solder bump to the under-bump metallization component.

4. The device of claim 1 , wherein the superconducting interconnect component comprises a hermetically sealed superconducting interconnect component.

5. The device of claim 1 , wherein the solder bump comprises at least one superconducting material.

6. A device, comprising:
a substrate having a superconducting layer and an intermetallic compound layer; and
a solder bump coupled to the superconducting layer and the intermetallic compound layer;
a first set of solder diffusion layers provided on a first set of respective portions of a second superconducting layer, and a second set of solder diffusion layers provided on a second set of respective portions of a third superconducting layer, wherein the solder is within a channel and is in direct contact with the second superconducting layer and the second third superconducting layer within the channel.

7. The device of claim 6 , wherein the superconducting layer is hermetically sealed by at least one of the intermetallic compound layer or the solder bump.

8. The device of claim 6 , further comprising a solder wetting layer coupled to the intermetallic compound layer and the superconducting layer, thereby facilitating at least one of improved mechanical coupling or improved electrical coupling of the solder bump to the superconducting layer.

9. A device, comprising:
a first under-bump metallization component comprising a superconducting interconnect component and an intermetallic compound layer; and
a solder bump coupled to the superconducting interconnect component, the intermetallic compound layer, and a second under-bump metallization component, wherein the solder is within a channel and is in direct contact with a plurality of superconducting layers within the channel.

10. The device of claim 9 , wherein the solder bump is coupled to a second superconducting interconnect component of the second under-bump metallization component.

11. The device of claim 9 , wherein the superconducting interconnect component comprises a hermetically sealed superconducting interconnect component.

12. The device of claim 9 , further comprising a mechanical interconnect component coupled to the first under-bump metallization component and the second under-bump metallization component.

13. The device of claim 12 , wherein the mechanical interconnect component comprises at least one of a stud bump or a plated pedestal.

Assignees

• IBM

Inventors

• Nah Jae-Woong
• Lewandowski Eric Peter
• Narasgond Adinath Shantinath

Classifications

• H10D64/01304

  characterised by the conductor · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title