Circuit substrate and semiconductor package structure

Patent metadata

Field	Value
Publication number	US-2016126175-A1
Application number	US-201514828758-A
Country	US
Kind code	A1
Filing date	Aug 18, 2015
Priority date	Nov 4, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface. A first through via plug passes through the core substrate. A first conductive line pattern and a second conductive line pattern adjacent to the first conductive line are disposed on the chip-side surface. A pad is disposed on the bump-side surface. The first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad. The first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type.

First claim

What is claimed is:

1 . A circuit substrate for a chip bonding thereon, comprising:
a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface; a first through via plug passing through the core substrate; a first conductive line pattern and a second conductive line pattern adjacent to the first conductive line disposed on the chip-side surface; and a pad disposed on the bump-side surface, wherein the first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad, and wherein the first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type.

2 . The circuit substrate as claimed in claim 1 , further comprising:
a conductive planar layer disposed on the chip-side surface, wherein the first through via plug is electrically connected to the conductive planar layer, and the first conductive line pattern is electrically connected to the second conductive line pattern through the conductive planar layer.

3 . The circuit substrate as claimed in claim 2 , wherein the first conductive line pattern, the second conductive line pattern and the conductive planar layer collectively form a first vent hole on the chip-side surface.

4 . The circuit substrate as claimed in claim 2 , wherein the conductive planar layer has a segment between the first conductive line pattern and the second conductive line pattern, wherein the conductive planar layer, the segment and the first conductive line pattern collectively form a second vent hole on the chip-side surface, wherein the conductive planar layer, the segment and the second conductive line pattern collectively form a third vent hole on the chip-side surface.

5 . The circuit substrate as claimed in claim 1 , further comprising:
a second through via plug and a third through via plug passing through the core substrate; a conductive planar layer disposed on the chip-side surface, wherein the conductive planar layer is in direct contact with and overlapping the second and third through via plugs; and a first thickness enhancing conductive pattern disposed on a surface of the conductive planar layer, which is away from the chip-side surface.

6 . The circuit substrate as claimed in claim 1 , further comprising:
a second thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.

7 . The circuit substrate as claimed in claim 6 , wherein the second thickness enhancing conductive pattern had a plurality of protruding portions, and the protruding portions have rotational symmetry with one another about a rotation axis passing through a center of the second thickness enhancing conductive pattern.

8 . The circuit substrate as claimed in claim 7 , wherein an angle between two of the adjacent protruding portions is greater than 90 degrees.

9 . The circuit substrate as claimed in claim 6 , wherein the second thickness enhancing conductive pattern comprises a center pillar and at least three peripheral pillars separated from the center pillar by a distance, respectively.

10 . The circuit substrate as claimed in claim 9 , wherein a corner portion of the peripheral pillars is close to the center pillar, and an angle of the corner portion is less than 90 degrees.

11 . The circuit substrate as claimed in claim 9 , wherein a pair of extension lines along a pair of opposite sides of one of the peripheral pillars crosses at a center of the center pillar, and an angle of the pair of extension lines is less than 90 degrees.

12 . A circuit substrate for a chip bonding thereon, comprising:
a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface; a first through via plug passing through the core substrate; a pad disposed on the bump-side surface, in contact with the first through via plug; and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.

13 . The circuit substrate as claimed in claim 12 , wherein the first thickness enhancing conductive pattern has a plurality of protruding portions, and the protruding portions have rotational symmetry with one another about a rotation axis passing through a center of the first thickness enhancing conductive pattern.

14 . The circuit substrate as claimed in claim 13 , wherein an angle between two of the adjacent protruding portions is greater than 90 degrees.

15 . The circuit substrate as claimed in claim 12 , wherein the first thickness enhancing conductive pattern comprises a center pillar and at least three peripheral pillars separated from the center pillar by a distance, respectively.

16 . The circuit substrate as claimed in claim 15 , wherein a corner portion of the peripheral pillars is close to the center pillar, and an angle of the corner portion is less than 90 degrees.

17 . The circuit substrate as claimed in claim 12 , wherein a pair of extension lines along a pair of opposite sides of one of the peripheral pillars crosses at a center of the center pillar, and an angle of the pair of extension lines is less than 90 degrees.

18 . The circuit substrate as claimed in claim 12 , further comprising:
a second through via plug passing through the core substrate; a conductive planar layer disposed on the chip-side surface, wherein the conductive planar layer is in direct contact with and overlapping the first and second through via plugs; and a second thickness enhancing conductive pattern disposed on a surface of the conductive planar layer, which is away from the chip-side surface.

19 . The circuit substrate as claimed in claim 18 , wherein a width of the second thickness enhancing conductive pattern is less than a width of the conductive planar layer.

20 . The circuit substrate as claimed in claim 18 , further comprising a conductive line pattern disposed on the chip-side surface, wherein the first through via plug and the second through via plug do not contact with the conductive line pattern.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Hsu Yeh-Chi
• Kung Chen-Yueh

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title