Systems and methods for testing and packaging a superconducting chip

Patent metadata

Field	Value
Publication number	US-9865648-B2
Application number	US-201314109604-A
Country	US
Kind code	B2
Filing date	Dec 17, 2013
Priority date	Dec 17, 2012
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.

First claim

The invention claimed is:

1. A method of testing and packaging a superconducting chip, wherein the superconducting chip includes at least one material that superconducts below a critical temperature, the method comprising:
forming a first set of superconducting solder bumps on the superconducting chip;
superconductively electrically coupling the superconducting chip to a testing module via the first set of superconducting solder bumps to form a testing assembly;
cooling the testing assembly to a first temperature below the critical temperature such that the superconducting chip superconducts;
testing electrical properties of the superconducting chip while the superconducting chip superconducts;
removing the superconducting chip from the testing assembly, wherein removing the superconducting chip from the testing assembly includes decoupling the superconducting chip from the testing module via the first set of superconducting solder bumps;
forming a second set of superconducting solder bumps on a chip packaging module; and
after removing the superconducting chip from the testing assembly, superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps.

2. The method of claim 1 wherein the testing module comprises a first set of superconducting bonding pads, each superconducting bonding pad in the first set of superconducting bonding pads including at least one layer of superconducting material, and wherein superconductively electrically coupling the superconducting chip to the testing module via the first set of superconducting solder bumps includes superconductively electrically coupling the superconducting chip to the first set of superconducting bonding pads via the first set of superconducting solder bumps.

3. The method of claim 2 wherein superconductively electrically coupling the superconducting chip to the testing module via the first set of superconducting solder bumps includes positioning the superconducting chip in physical contact with the testing module such that each superconducting solder bump in the first set of superconducting solder bumps aligns with and forms a superconductive electrical connection to a respective superconducting bonding pad in the first set of superconducting bonding pads.

4. The method of claim 2 wherein the superconducting chip comprises a second set of superconducting bonding pads, each superconducting bonding pad in the second set of superconducting bonding pads including at least one layer of superconducting material, and wherein superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps includes superconductively electrically coupling the superconducting chip to the second set of superconducting bonding pads via the second set of superconducting solder bumps.

5. The method of claim 4 wherein superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps includes positioning the superconducting chip in physical contact with the chip packaging module such that each superconducting solder bump in the second set of superconducting solder bumps aligns with and forms a superconductive electrical connection to a respective superconducting bonding pad in the second set of superconducting bonding pads.

6. The method of claim 1 wherein the superconducting chip comprises a superconducting quantum processor.

7. The method of claim 1 wherein the testing module is a multi-chip module.

8. The method of claim 1 wherein superconductively electrically coupling the superconducting chip to the testing module via the first set of superconducting solder bumps includes superconductively electrically coupling the superconducting chip to the testing module via a solder reflow process.

9. The method of claim 1 wherein superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps includes superconductively electrically coupling the superconducting chip to the chip packaging module via a solder reflow process.

10. The method of claim 1 , further comprising:
cooling the chip packaging module to a second temperature below the critical temperature such that the superconducting chip superconducts.

11. The method of claim 10 wherein the second temperature is lower than the first temperature.

12. The method of claim 1 wherein:
superconductively electrically coupling the superconducting chip to the testing module via the first set of superconducting solder bumps includes forming a first set of continuous, uninterrupted superconducting signal paths between the superconducting chip and the testing module; and
superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps includes forming a second set of continuous, uninterrupted superconducting signal paths between the superconducting chip and the chip packaging module.

13. A method of testing and packaging a superconducting chip, wherein the superconducting chip includes at least one material that superconducts below a critical temperature, the method comprising:
forming a first set of superconducting solder bumps on a testing module;
superconductively electrically coupling the superconducting chip to the testing module via the first set of superconducting solder bumps to form a testing assembly;
cooling the testing assembly to a first temperature below the critical temperature such that the superconducting chip superconducts;
testing electrical properties of the superconducting chip while the superconducting chip superconducts;
removing the superconducting chip from the testing assembly, wherein removing the superconducting chip from the testing assembly includes decoupling the superconducting chip from the testing module via the first set of superconducting solder bumps;
forming a second set of superconducting solder bumps on a chip packaging module; and
after removing the superconducting chip from the testing assembly, superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps.

14. The method of claim 13 wherein the superconducting chip comprises a first set of superconducting bonding pads, each superconducting bonding pad in the first set of superconducting bonding pads including at least one layer of superconducting material, and wherein superconductively electrically coupling the superconducting chip to the testing module via the first set of superconducting solder bumps includes superconductively electrically coupling the testing module to the first set of superconducting bonding pads via the first set of superconducting solder bumps.

15. The method of claim 14 wherein superconductively electrically coupling the superconducting chip to the testing module via the first set of superconducting solder bumps includes positioning the superconducting chip in physical contact with the testing module such that each superconducting solder bump in the first set of superconducting solder bumps aligns with and forms a superconductive electrical connection to a respective superconducting bonding pad in the first set of superconducting bonding pads.

16. The method of claim 14 wherein superconductively electrically coupling the superconducting chip to the chip packaging module via the second set of superconducting solder bumps includes sup

Assignees

• D Wave Systems Inc

Inventors

• Bunyk Paul I

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title