Semiconductor devices and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11735627-B2
Application number	US-202117324610-A
Country	US
Kind code	B2
Filing date	May 19, 2021
Priority date	Sep 28, 2020
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a device isolation layer on the substrate;
a plurality of pattern groups each including fin patterns extending from the substrate, the fin patterns protruding farther upward than an upper surface of the device isolation layer, and the fin patterns extending in a first direction; and
gate structures on the substrate, the gate structures intersecting the fin patterns and the gate structures extending in a second direction intersecting the first direction,
wherein the plurality of pattern groups include a first pattern group including first fin patterns,
wherein at least one pair of the first fin patterns are arranged with a first pitch in the second direction and the first pitch is a minimum pitch in the second direction of the first fin patterns,
wherein the first pattern group includes a first recess portion and a first planar portion of the substrate, the first recess portion has a central axis spaced apart by a first distance in the second direction from a central axis of a corresponding first fin pattern among the first fin patterns, the first planar portion extends from the first recess portion and has a first width in the second direction,
wherein the first distance is about 0.8 times to about 1.2 times the first pitch, and
wherein the first width is greater than the first pitch.

2. The semiconductor device of claim 1 , wherein the first recess portion includes:
double-humped protrusions protruding upwardly towards the upper surface of the device isolation layer; and
a recessed concave portion between the double-humped protrusions.

3. The semiconductor device of claim 2 , wherein
the double-humped protrusions include a first protrusion and a second protrusion,
the first protrusion is adjacent to the corresponding first fin pattern and has a first upper end,
the second protrusion is adjacent to the first planar portion and has a second upper end,
the first upper end is spaced apart from the central axis of the corresponding first fin pattern by a first spacing in the second direction,
the second upper end is spaced apart from the central axis of the corresponding first fin pattern by a second spacing in the second direction,
the first spacing is about 0.5 times to about 0.8 times the first pitch, and
the second spacing is about 1.2 times to about 1.5 times the first pitch.

4. The semiconductor device of claim 2 , wherein
a lower end of the recessed concave portion is in the substrate at a level lower than a level of an upper end of the corresponding first fin pattern by about 60 nm or more.

5. The semiconductor device of claim 2 ,
wherein the first recess portion is connected to one end of the first planar portion,
wherein the first pattern group includes a second recess portion of the substrate that is recessed in the substrate and connected to an other end of the first planar portion,
wherein a central axis of the second recess portion is spaced apart from an other first fin pattern among the first fin patterns of the first pattern group by a third distance in the second direction, and
wherein the third distance is about 0.8 times to about 1.2 times the first pitch.

6. The semiconductor device of claim 5 , wherein the second recess portion includes:
double-humped protrusions protruding upwardly towards the upper surface of the device isolation layer; and
a recessed concave portion between the double-humped protrusions of the second recess portion.

7. The semiconductor device of claim 5 , wherein the first planar portion has a substantially planar surface.

8. The semiconductor device of claim 1 , wherein a lower end of the first recess portion is in the substrate at a level lower than a surface of the first planar portion.

9. The semiconductor device of claim 8 , wherein the first recess portion has a trench shape in the substrate that is concave downwardly without a sharp protrusion.

10. The semiconductor device of claim 1 ,
wherein the first recess portion is connected to one end of the first planar portion,
wherein the first pattern group includes a second recess portion of the substrate that is recessed in the substrate and connected to an other end of the first planar portion,
wherein a central axis of the second recess portion is spaced apart from an other first fin pattern among the first fin patterns of the first pattern group by a third distance in the second direction,
wherein the third distance is about 0.8 times to about 1.2 times the first pitch, and
wherein a lower end of the first recess portion and a lower end of the second recess portion are in the substrate at a level lower than a surface of the first planar portion.

11. The semiconductor device of claim 1 , further comprising:
a plurality of channel layers spaced apart from each other in a vertical direction on each of the first fin patterns,
wherein each of the plurality of channel layers are surrounded by a gate dielectric layer and a gate electrode of a corresponding gate structure among the gate structures.

12. The semiconductor device of claim 1 ,
wherein the plurality of pattern groups include a second pattern group including second fin patterns arranged with a second pitch greater than the first pitch in the second direction,
wherein the second fin patterns include two adjacent second fin patterns,
wherein the second pattern group includes a second recess portion of the substrate,
the second recess portion has a central axis spaced apart from a central axis of one of the two adjacent second fin patterns taken in the second direction by a second distance in the second direction between the two adjacent second fin patterns,
the second recess portion is recessed in the substrate, and
wherein the second distance is less than the second pitch.

13. A semiconductor device, comprising:
a substrate;
a device isolation layer on the substrate;
a pattern group including fin patterns extending in a first direction on the substrate; and
a gate structure on the substrate, the gate structure intersecting the fin patterns and extending in a second direction perpendicular to the first direction,
wherein the fin patterns of the pattern group include a first fin pattern and a second fin pattern arranged with a minimum pitch in the second direction,
wherein the pattern group includes a first recess portion and a second recess portion of the substrate that are recessed in the substrate,
wherein the first fin pattern and the second fin pattern are between the first recess portion and the second recess portion,
wherein the first recess portion and the second recess portion are adjacent to the first fin pattern and the second fin pattern, respectively,
wherein the pattern group further includes a planar portion of the substrate, the planar portion extending from at least one of the first recess portion and the second recess portion, and the planar portion having a substantially planar surface, and
wherein a width of the substantially planar surface of the planar portion in the second direction is greater than the minimum pitch.

14. The semiconductor device of claim 13 , wherein the width of the substantially planar surface of the planar portion is about 2 times greater than the minimum pitch and about 4 times less than the minimum pitch.

15. The semiconductor device of claim 14 , wherein at least one of the first recess portion and the second recess portion has a lower end at a first depth from an upper surface of the device isolation layer.

16. The semiconductor device of claim 15 , wherein the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jongsoon
• Park Jongchul
• Lee Bokyoung
• Lee Jeongyun
• Lee Hyunggoo
• Jung Yeondo
• Jung Haegeon

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title