Field effect transistor having fin base and at lease one fin protruding from fin base

Patent metadata

Field	Value
Publication number	US-8987836-B2
Application number	US-201313780855-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Apr 23, 2012
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

First claim

What is claimed is:

1. A field effect transistor, comprising:
a source region and a drain region on a substrate;
a fin base protruding from a top surface of the substrate;
a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region;
a gate electrode on the plurality of fin portions;
a gate dielectric between the plurality of fin portions and the gate electrode; and
a device isolation layer exposing upper portions of the plurality of fin portions and covering the top surface of the substrate adjacent to the fin base,
wherein the top surface of the substrate adjacent to the fin base includes a plurality of grooves, and each of the plurality of grooves includes a plurality of convex portions and a plurality of concave portions extending along an extending direction of the plurality of fin portions.

2. The field effect transistor of claim 1 , wherein a thickness of the fin base is greater than half a depth of a first trench between the plurality of fin portions.

3. The field effect transistor of claim 1 , further comprising:
at least one first trench between the plurality of fin portions,
wherein top surfaces of the plurality of convex portions are lower than a bottom surface of the at least one first trench.

4. The field effect transistor of claim 1 , further comprising:
at least one first trench between the plurality of fin portions,
wherein top surfaces of the plurality of convex portions are higher than a bottom surface of the at least one first trench.

5. The field effect transistor of claim 1 , further comprising:
at least one first trench between the plurality of fin portions,
wherein a top surface of the device isolation layer is higher than a bottom surface of the at least one first trench.

6. The field effect transistor of claim 1 , wherein a distance between the plurality of convex portions is substantially equal to a distance between the plurality of fin portions.

7. The field effect transistor of claim 1 , wherein the plurality of convex portions and the plurality of concave portions alternate each other assimilating a line-and-space pattern of the plurality of fin portions.

8. The field effect transistor of claim 1 , wherein the plurality of fin portions include a first fin portion and second fin portions, the second fin portions being outside the first fin portion and adjacent to the plurality of grooves, and the first and second fin portions have a substantially same width.

9. A field effect transistor, comprising:
at least one fin portion extending from a top surface of a substrate;
a device isolation layer exposing an upper portion of the at least one fin portion;
a gate electrode on and crossing the at least one fin portion; and
a gate dielectric between the at least one fin portion and the gate electrode,
wherein the top surface of the substrate includes a plurality of grooves, each of the plurality of grooves includes a plurality of convex portions and a plurality of concave portions, the plurality of convex portions extend parallel to the at least one fin portion, and the device isolation layer covers top surfaces of the plurality of convex portions.

10. The field effect transistor of claim 9 , wherein the at least one fin portion includes a plurality of fin portions spaced apart from, each other by at least one first trench therebetween, and
further comprising:
a fin base extending from the top surface of the substrate and connected to bottom surfaces of the plurality of the fin portions.

11. The field effect transistor of claim 10 , wherein a top surface of the fin base is defined by a bottom surface of the at least one first trench, and
the bottom surface of the at least one first trench is higher than top surfaces of the plurality of convex portions.

12. The field effect transistor of claim 10 , wherein a top surface of the fin base is defined by a bottom surface of the at least one first trench, and
the bottom surface of the at least one first trench is lower than top surfaces of the plurality of convex portions.

13. The field effect transistor of claim 10 , wherein the plurality of the fin portions connect a source region with a drain region, and
upper portions of the plurality of the fin portions have a substantially same width as each other.

14. The field effect transistor of claim 9 , wherein the substrate includes a first region and a second region, and
a number of the at least one fin portion in the first region is different than a number of the at least one fin portion in the second region.

15. A field effect transistor, comprising:
a substrate having a substrate body, at least one fin portion extending away from a surface of the substrate body, and a fin base interposed between the substrate body and the at least one fin portion;
a source region and a drain region connected to each other via the at least one fin portion;
a gate electrode over the at least one fin portion;
a gate dielectric between the at least one fin portion and the gate electrode; and
a device isolation layer exposing an upper portion of the at least one fin portion and covering a top surface of the substrate body adjacent to the fin base,
wherein the top surface of the substrate body adjacent to the fin body includes a plurality of grooves, each of the plurality of grooves includes a plurality of convex portions and a plurality of concave portions, and the plurality of convex portions extend from the surface of the substrate body and are parallel to the at least one fin portion.

16. The field effect transistor of claim 15 , wherein the at least one fin portion includes a plurality of fin portions having a same width and spaced apart from each other.

17. The field effect transistor of claim 16 , wherein the plurality of fin portions are symmetrical.

18. The field effect transistor of claim 16 , wherein,
either the plurality of grooves extends above the fin base or the fin base extends above the plurality of grooves.

19. The field effect transistor of claim 18 , wherein a thickness of the fin base is less than half a depth of a first trench between adjacent fin portions when the plurality of grooves extend above the fin base, or the thickness of the fin base is greater than half the depth of the first trench when the fin base extends above the plurality of grooves.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Myeong-Cheol
• Kim Cheol
• Seo Jaehun
• Lee Yoojung
• Chang Kisoo
• Choi Siyoung

Classifications

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6211 Primary

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/7851

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic