Method of manufacturing semiconductor device and semiconductor device by the same

Patent metadata

Field	Value
Publication number	US-10522364-B2
Application number	US-201816051683-A
Country	US
Kind code	B2
Filing date	Aug 1, 2018
Priority date	Jan 17, 2018
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method including forming hard mask patterns on a substrate; forming etch stop patterns surrounding the hard mask patterns; forming spacer patterns covering sidewalls of the etch stop patterns; removing the etch stop patterns; etching the substrate to form active and dummy fins; forming a block mask pattern layer surrounding the active and dummy fins and forming mask etch patterns on a top surface of the block mask pattern layer; etching the block mask pattern layer to form block mask patterns surrounding the active fins; etching the dummy fins; removing the block mask patterns surrounding the active fins; and depositing a device isolation film on the substrate such that the device isolation film is not in contact with the upper portions of the active fins, wherein a spacing distance between the active fin and the dummy fin is greater than an active fin spacing distance between the active fins.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming hard mask patterns on a substrate such that forming the hard mask pattern includes forming a plurality of hard mask units, each hard mask unit having at least two hard mask patterns that are spaced a pattern spacing distance from each other and the hard mask units being separated from each other by a spacing distance that is greater than the pattern spacing distance;
forming etch stop patterns surrounding the hard mask patterns of the hard mask units;
forming spacer patterns covering sidewalls of the etch stop patterns;
removing the etch stop patterns;
etching the substrate using the hard mask patterns and the spacer pattern as etch masks to form at least one active fin unit that includes at least two active fins and to form dummy fins disposed on both sides of the at least one active fin unit;
forming a block mask pattern layer surrounding the active fins and the dummy fins and forming mask etch patterns in regions including upper portions of the active fins on a top surface of the block mask pattern layer;
etching the block mask pattern layer using the mask etch patterns to form block mask patterns surrounding the active fins;
etching the dummy fins using the block mask patterns;
removing the block mask patterns surrounding the active fins; and
depositing a device isolation film on the substrate such that the device isolation film is not in contact with the upper portions of the active fins,
wherein a spacing distance between one active fin and an adjacent dummy fin is greater than an active fin spacing distance between adjacent active fins.

2. The method as claimed in claim 1 , wherein a width from a sidewall of each of the etch stop patterns to an outer sidewall of the hard mask pattern disposed at an outermost side of the hard mask unit is greater than the pattern spacing distance.

3. The method as claimed in claim 1 , wherein the spacing distance between the active fin and the dummy fin is 1.1 times to 3 times the active fin spacing distance.

4. The method as claimed in claim 1 , wherein each etch stop pattern is separated from a neighboring etch stop pattern by a distance corresponding to at least a width of the spacer pattern.

5. The method as claimed in claim 1 , wherein the spacer pattern is formed by overlapping at least a portion of a neighboring spacer pattern.

6. The method as claimed in claim 1 , wherein a width of the spacer pattern is greater than a width of the hard mask pattern.

7. The method as claimed in claim 1 , wherein a width of the dummy fin is greater than a width of the active fin.

8. The method as claimed in claim 1 , wherein the dummy fins are etched and maintained to have a smaller height than a top surface of the device isolation film.

9. The method as claimed in claim 1 , wherein:
the at least one active fin unit includes a plurality of active fin units, and
one of the active fin units includes a different number of active fins from another active fin unit.

10. The method as claimed in claim 1 , wherein the device isolation film is formed to not be in contact with top surfaces and upper portion of both side surfaces of the active fins.

11. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of hard mask units on a substrate such that each of the hard mask units includes at least two hard mask patterns spaced a pattern spacing distance from each other on an upper portion of the substrate;
forming a plurality of spacer patterns on the substrate such that the spacer patterns are outside the hard mask units; and
forming active fins and dummy fins by etching the substrate using the hard mask patterns and the spacer patterns as etch masks,
wherein:
a spacing distance between one active fin and an adjacent dummy fin is greater than a spacing distance between adjacent active fins, and
a width of each dummy fin is greater than a width of each active fin.

12. The method as claimed in claim 11 , wherein a width of the spacer patterns is greater than a width of the hard mask patterns.

13. The method as claimed in claim 11 , wherein the spacer patterns are formed by overlapping at least a portion of a neighboring spacer pattern.

14. A semiconductor device prepared according to the method as claimed in claim 1 .

15. The semiconductor device as claimed in claim 14 , wherein the spacing distance between the active fin and the dummy fin is 1.1 times to 3 times the active fin spacing distance.

16. The semiconductor device as claimed in claim 14 , wherein a width of the dummy fin is greater than a width of the active fin.

17. The semiconductor device as claimed in claim 14 , wherein at least one of the dummy fins has a different width from the remaining dummy fins.

18. The semiconductor device as claimed in claim 14 , wherein the device isolation film is not in contact with top surfaces of the active fins.

19. The semiconductor device as claimed in claim 14 , further comprising:
a gate electrode surrounding top surfaces and part of both side surfaces of the active fins that protrude upwardly from the device isolation film, and the gate electrode crossing the active fins;
a gate insulating film between the gate electrode and the active fins; and
a source and drain region in the active fins exposed on both sides of the gate electrode in regions at which the active fins intersect the gate electrode.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sung Min
• Kim Dong Won

Classifications

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H01L21/3086 Primary

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L29/6681

  Electricity · mapped topic