Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11721740-B2
Application number	US-202117396783-A
Country	US
Kind code	B2
Filing date	Aug 9, 2021
Priority date	Nov 15, 2017
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Provided is a semiconductor device including a first n-type transistor comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second n-type transistor comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first n-type transistor comprising a first work function layer, the first work function layer comprising a first underlying layer; and
a second n-type transistor comprising a second work function layer, the second work function layer comprising a second underlying layer,
wherein the first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer.

2. The semiconductor device of claim 1 , wherein the at least two kinds of metals comprise a first metal comprising Ti, Ta, or a combination thereof, and a second metal comprising Al, Ta, W, or a combination thereof.

3. The semiconductor device of claim 2 , wherein a content of the second metal in the first underlying layer or the second underlying layer is in the range of 10 wt % and 18 wt %.

4. The semiconductor device of claim 1 , wherein the first work function layer further comprises a first overlying layer overlaying the first underlying layer, the second work function layer further comprises a second overlying layer overlaying the second underlying layer, and the first and second overlying layers each comprises TiAl, TaAl, HfAl, or a combination thereof.

5. The semiconductor device of claim 1 , further comprising a third n-type transistor comprising a third work function layer, wherein third work function layer comprises a third overlying layer, and the third overlying layer comprises TiAl, TaAl, HfAl, or a combination thereof.

6. The semiconductor device of claim 5 , wherein the first n-type transistor has a threshold voltage Vn1, the second n-type transistor has a threshold voltage Vn2, the third n-type transistor has a threshold voltage Vn3, and 0<Vn3<Vn2<Vn1.

7. The semiconductor device of claim 1 , further comprising:
a first p-type transistor with a threshold voltage Vp1 comprising a fourth work function layer;
a second p-type transistor with a threshold voltage Vp2 comprising a fifth work function layer; and
a third p-type transistor with a threshold voltage Vp3 comprising a sixth work function layer, wherein Vp1<Vp2<Vp3<0, a thickness of the sixth work function layer is greater than a thickness of the fifth work function layer, and the thickness of the fifth work function layer is greater than a thickness of the fourth work function layer.

8. A semiconductor device, comprising:
a p-type FinFET comprising a first gate structure between a pair of first source and/or drain (S/D) regions, the first gate structure comprising:
a first gate dielectric layer;
a first metal filling layer over the first gate dielectric layer; and
a first work function layer between the first gate dielectric layer and the first metal filling layer, wherein the first work function layer is selected from a first material in which a threshold voltage of the p-type FinFET decreases as a thickness of the first work function layer increases.

9. The semiconductor device of claim 8 , further comprising a barrier layer and an adhesive layer, wherein the first work function layer is disposed between the barrier layer and the adhesive layer.

10. The semiconductor device of claim 9 , wherein the first work function layer comprises a first layer and a second layer underlying the first layer, the first layer comprises TiAl, TaAl, HfAl, or a combination thereof, and the second layer comprises a metal nitride layer with at least two kinds of metals.

11. The semiconductor device of claim 10 , wherein the first layer is between and in contact with the second layer and the adhesive layer, and the second layer is between and in contact with the barrier layer and the first layer.

12. The semiconductor device of claim 10 , wherein the at least two kinds of metals comprises a first metal comprising Ti, Ta, or a combination thereof, and a second metal comprising Al, Ta, W, or a combination thereof.

13. The semiconductor device of claim 8 , further comprising:
a n-type FinFET comprising a second gate structure between a pair of second source and/or drain (S/D) regions, the second gate structure comprising:
a second gate dielectric layer;
a second metal filling layer over the second gate dielectric layer; and
a second work function layer between the second gate dielectric layer and the second metal filling layer, wherein the second work function layer is selected from a second material in which a threshold voltage of the n-type FinFET increases as a thickness of the second work function layer increases.

14. A method of manufacturing a gate structure for a semiconductor device, comprising:
providing a substrate at least having a first region and a second region;
forming a first gate structure having a first work function layer over the first region for a first n-type transistor; and
forming a second gate structure having a second work function layer over the second region for a second n-type transistor,
wherein the first work function layer comprises a first underlying layer and the second work function layer comprises a second underlying layer having a thickness less than a thickness of the first underlying layer,
wherein each of the first and second underlying layers is doped with a dopant in a base material by an atomic layer deposition (ALD) method, and the dopant comprises Al, Ta, W or a combination thereof.

15. The method of claim 14 , wherein the first work function layer further comprises a first overlying layer formed on the first underlying layer, and the first overlying layer comprises TiAl, TaAl, HfAl, or a combination thereof.

16. The method of claim 14 , wherein the second work function layer further comprises a second overlying layer formed on the second underlying layer, and the second overlying layer comprises TiAl, TaAl, HfAl, or a combination thereof.

17. The method of claim 14 , wherein doping the each of the first and second underlying layers with the dopant in the base material by the ALD method comprises:
performing a first cycle to introduce a nitrogen precursor and a first metal precursor to form a metal nitride layer; and
performing a second cycle to introduce a second metal precursor on a surface of the metal nitride layer.

18. The method of claim 17 , wherein the nitrogen precursor comprises NH 3 , N 2 , N 2 O, or a combination thereof, the first metal precursor comprises TiCl 4 , TaCl 5 , or a combination thereof, the second metal precursor comprises trimethylaluminium (TMA), aluminium chloride (AlCl 3 ), triisobutylaluminum (TIBA, Al(CH 2 CH(CH 3 ) 2 ) 3 ), WF 6 , TaCl 5 , or a combination thereof.

19. The method of claim 14 , wherein doping the one of the first, second, and third work function layers with the dopant in the base material by the ALD method comprises:
performing a first cycle to introduce a first nitrogen precursor and a first metal precursor to form a metal nitride layer; and
performing a third cycle to introduce a second nitrogen precursor and a second metal precursor on a surface of the metal nitride layer.

20. The method of claim 19 , wherein each of the first and second nitrogen precursors comprises NH 3 , N 2 , N 2 O, or a combination thereof, the first metal precursor comprises TiCl 4 , TaCl 5 , or a combination thereof, the second metal precursor comprises trimethylaluminium (TMA), aluminium chloride (AlCl 3 ), triisobutylaluminum (TIBA, Al(CH 2 CH(CH 3 ) 2 ) 3 ), WF 6 , TaCl 5 , or a combination thereof.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• CHIEN Jui-Fen
• Wei Hsiao-Kuan
• Lee Hsien-Ming
• Hsu Chin-You

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title