Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11716839-B2
Application number	US-202117357139-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Nov 9, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

First claim

What is claimed is:

1. A semiconductor device comprising:
an active pattern on a substrate; a gate structure buried at an upper portion of the active pattern;
a bit line structure having a first conductive pattern, wherein a lowermost portion of the first conductive pattern is in direct contact with an upper surface of the active pattern;
a lower spacer structure covering a lower sidewall of the bit line structure;
a contact plug structure on the active pattern and adjacent to the bit line structure; and a capacitor on the contact plug structure,
wherein,
the lower spacer structure includes a first lower spacer and a second lower spacer that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is parallel to an upper surface of the substrate,
the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and
the second lower spacer includes a material different from any of the materials of the first lower spacer.

2. The semiconductor device of claim 1 , wherein the first lower spacer includes an oxide.

3. The semiconductor device of claim 1 , wherein the second lower spacer includes a nitride.

4. The semiconductor device of claim 1 , wherein the second lower spacer contacts the contact plug structure.

5. The semiconductor device of claim 1 , further comprising:
an isolation pattern covering the active pattern,
wherein at least one of (a) the second lower spacer contacts the active pattern or (b) the second lower spacer contacts the isolation pattern.

6. The semiconductor device of claim 1 , wherein the bit line structure includes the first conductive pattern, a diffusion barrier, a second conductive pattern, and a capping pattern that are sequentially stacked in a vertical direction that is perpendicular to the upper surface of the substrate, and
the first conductive pattern includes polysilicon having n-type impurities.

7. The semiconductor device of claim 6 , wherein the first lower spacer contacts a sidewall of the first conductive pattern.

8. The semiconductor device of claim 1 , further comprising:
an upper spacer structure covering an upper sidewall of the bit line structure.

9. The semiconductor device of claim 8 , wherein the upper spacer structure includes a first upper spacer, a second upper spacer, and a third upper spacer that are sequentially stacked from the upper sidewall of the bit line structure in the horizontal direction, and
the first upper spacer contacting the upper sidewall of the bit line structure includes a nitride.

10. The semiconductor device of claim 9 , wherein the second upper spacer is an air spacer including air, and
the third upper spacer includes a nitride.

11. The semiconductor device of claim 9 , wherein upper surfaces of the second and third upper spacers are lower than an upper surface of the first upper spacer.

12. A semiconductor device comprising:
an active pattern on a substrate;
a gate structure buried at an upper portion of the active pattern;
a bit line structure having a first conductive pattern, wherein a lowermost portion of the first conductive pattern is in direct contact with an upper surface of the active pattern, the bit line structure including the first conductive pattern, a diffusion barrier, a second conductive pattern, and a capping pattern that are sequentially stacked in a vertical direction that is perpendicular to an upper surface of the substrate;
a lower spacer structure covering a sidewall of at least a portion of the first conductive pattern of the bit line structure;
an upper spacer structure on the lower spacer structure, the upper spacer structure covering a sidewall of other portions of the bit line structure;
a contact plug structure on the active pattern and adjacent to the bit line structure; and
a capacitor on the contact plug structure,
wherein,
the first conductive pattern includes polysilicon having n-type impurities, and
the second conductive pattern includes a metal,
the lower spacer structure includes a first lower spacer and a second lower spacer that are sequentially stacked from the sidewall of the at least a portion of the first conductive pattern in a horizontal direction that is parallel to the upper surface of the substrate,
the first lower spacer includes an oxide, and covers the sidewall of the at least a portion of the first conductive pattern, but does not contact the contact plug structure,
the second lower spacer includes a nitride, and contacts the contact plug structure, and
the upper spacer structure contacting the sidewall of the other portions of the bit line structure includes a nitride.

13. The semiconductor device of claim 12 , wherein the first lower spacer contacts the sidewall of the at least a portion of the first conductive pattern.

14. The semiconductor device according to claim 12 , wherein the upper spacer structure includes a first upper spacer, a second upper spacer, and a third upper spacer that are sequentially stacked in the horizontal direction, and
the first upper spacer of the upper spacer structure contacts the sidewall of the other portions of the bit line structure.

15. The semiconductor device according to claim 14 , wherein the second upper spacer is an air spacer including air, and
the third upper spacer includes a nitride.

16. A semiconductor device comprising:
an active pattern on a substrate;
a gate structure buried at an upper portion of the active pattern, the gate structure extending in a first direction that is parallel to an upper surface of the substrate;
a bit line structure extending in a second direction and contacting the active pattern on a recess on a central upper surface of the active pattern, the second direction being parallel to the upper surface of the substrate and perpendicular to the first direction, the bit line structure including a first conductive pattern, a diffusion barrier, a second conductive pattern, and a capping pattern that are sequentially stacked in a vertical direction that is perpendicular to the upper surface of the substrate;
a lower spacer structure covering a sidewall of at least a portion of the first conductive pattern of the bit line structure, the lower spacer structure including a first lower spacer and a second lower spacer that are sequentially stacked in a horizontal direction that is parallel to the upper surface of the substrate;
an upper spacer structure covering a sidewall of a portion of the bit line structure not covered by the lower spacer structure, the upper spacer structure including a first upper space, a second upper spacer, and a third upper spacer that are sequentially stacked in the horizontal direction;
a contact plug structure on a corresponding one of opposite ends of the active pattern, the contact plug structure including a lower contact plug, an ohmic contact pattern, a barrier layer and an upper contact plug sequentially stacked in the vertical direction; and
a capacitor on the contact plug structure,
wherein the first lower spacer includes an oxide, and contacts the sidewall of the at least a portion of the first conductive pattern, but does not contact the contact plug structure, and
the second lower spacer includes a material different from any of the materials of the first lower spacer.

17. The semiconductor device of claim 16 , wherein the first lower spacer includes an oxide.

18. The semiconductor device of claim 16 , wherein the second lower spacer includes a ni

Assignees

• Samsung Electronics Co Ltd

Inventors

• Rhee Joonkyu
• Ahn Jiyoung
• Kim Hyunyong
• KOO Jamin
• Ahn Yongseok
• Um Minsub
• Lee Sangho
• Choi Yoonyoung

Classifications

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/0335 Primary

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/482

  Bit lines · CPC title