Semiconductor device for reducing coupling capacitance

Patent metadata

Field	Value
Publication number	US-9419002-B2
Application number	US-201414473139-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Feb 14, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.

First claim

What is claimed is:

1. A semiconductor device comprising:
a bit line contact;
a bit line disposed on the bit line contact and electrically connected to the bit line contact; and
a spacer disposed on a sidewall of the bit line contact and a sidewall of the bit line,
wherein the spacer has a structure in which a first spacer with a first dielectric constant, a second spacer with a second dielectric constant, a third spacer with a third dielectric constant, and a protecting spacer with a fourth dielectric constant are stacked, the second spacer having a different dielectric constant from those of the first, third, and protecting spacers, the protecting spacer having a same dielectric constant as those of the first and third spacers, the protecting spacer capping a lower portion of the second spacer.

2. The semiconductor device of claim 1 , wherein the first spacer includes a nitride layer.

3. The data semiconductor device of claim 1 , wherein the second spacer includes an oxide layer.

4. The semiconductor device of claim 3 , wherein the oxide layer is formed by transforming a portion of the first spacer.

5. The semiconductor device of claim 1 , wherein the protecting spacer contacts a surface of the lower portion of the second spacer.

6. The semiconductor device of claim 1 , wherein the first spacer is a first nitride layer, the second spacer is an oxide layer disposed on the first nitride layer, and the third spacer is a second nitride layer disposed on the oxide layer.

7. The semiconductor device of claim 1 , wherein the bit line contact has the substantially same width as the bit line.

Assignees

• Sk Hynix Inc

Inventors

• Han Ky Hyun
• Park Chang Heon
• Choi Dong Gu

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title