Semiconductor memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10074656-B1
Application number	US-201715479294-A
Country	US
Kind code	B1
Filing date	Apr 5, 2017
Priority date	Mar 9, 2017
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor memory device, comprising:
providing a semiconductor substrate;
forming a plurality of bit line structures on the semiconductor substrate, wherein each of the bit line structures is elongated in a first direction;
forming a first sidewall spacer on sidewalls of each of the bit line structures;
forming a plurality of storage node contacts on the semiconductor substrate, wherein some of the storage node contacts are repeatedly arranged in the first direction;
forming a conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts;
performing a first patterning process to the conductive layer for forming a plurality of stripe contact structures, wherein each of the stripe contact structures is elongated in the first direction and formed corresponding to a plurality of the storage node contacts, the first sidewall spacer formed at a first side of each of the bit line structures in a second direction is exposed by the first patterning process, and the first sidewall spacer formed at a second side of each of the bit line structures which is opposite to the first side in the second direction is covered by the stripe contact structures;
removing the first sidewall spacer exposed by the first patterning process for forming a plurality of first air spacers;
performing a second patterning process to the stripe contact structures for forming a plurality of storage node contact pads after the step of forming the first air spacers, wherein each of the storage node contact pads is formed corresponding to one of the storage node contacts, and each of the storage node contact pads is electrically connected with the corresponding storage node contact, wherein the first sidewall spacer formed at the second side of each of the bit line structures is partially covered by the storage node contact pads; and
removing the first sidewall spacer which is formed at the second side of each of the bit line structures and is not covered by the storage node contact pads for forming second air spacers after the step of forming the storage node contact pads, wherein at least a part of the second air spacers are repeatedly disposed in the first direction, and a part of the first sidewall spacer is disposed between the second air spacers adjacent to one another in the first direction.

2. The manufacturing method of the semiconductor memory device according to claim 1 , wherein a length of each of the first air spacers in the first direction is longer than a length of each of the storage node contact pads in the first direction.

3. The manufacturing method of the semiconductor memory device according to claim 1 , wherein a length of each of the second air spacers in the first direction is shorter than a length of each of the first air spacers in the first direction.

4. The manufacturing method of the semiconductor memory device according to claim 1 , wherein each of the first air spacers is elongated in the first direction.

5. The manufacturing method of the semiconductor memory device according to claim 1 , wherein the first patterning process comprises:
etching the conductive layer for forming the stripe contact structures;
forming a dielectric layer covering the stripe contact structures after the step of forming the stripe contact structures; and
performing an etching back process to the dielectric layer for exposing the first sidewall spacer formed at the first side of each of the bit line structures.

6. The manufacturing method of the semiconductor memory device according to claim 1 , further comprising:
forming at least one gate structure on the semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate, the bit lines structures and the storage node contacts are formed in the memory cell region, and the gate structure is formed in the peripheral region, wherein the conductive layer further covers the gate structure.

7. The manufacturing method of the semiconductor memory device according to claim 6 , wherein the conductive layer disposed on the gate structure is patterned by the first patterning process for forming a gate contact structure.

8. The manufacturing method of the semiconductor memory device according to claim 6 , further comprising:
patterning the conductive layer disposed on the gate structure for forming a gate contact structure after the first patterning process.

9. The manufacturing method of the semiconductor memory device according to claim 1 , further comprising:
forming a second sidewall spacer and a third sidewall spacer on the sidewalls of the bit line structures, wherein the second sidewall spacer is disposed between the first sidewall spacer and each of the bit line structures, and the first sidewall spacer is disposed between the second sidewall spacer and the third sidewall spacer.

10. The manufacturing method of the semiconductor memory device according to claim 9 , wherein the first sidewall spacer comprises an oxide spacer, and the second sidewall spacer and the third sidewall spacer comprise a nitride spacer respectively.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Wang Ying-Chiao
• Feng li-wei
• Ho Chien-Ting
• Lu Wen-Chieh
• Liu Li-Wei

Classifications

• H01L27/10888

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic

• H01L27/10894

  Electricity · mapped topic

• H01L27/10885 Primary

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic