Semiconductor device with air gap and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10622249-B2
Application number	US-201815990254-A
Country	US
Kind code	B2
Filing date	May 25, 2018
Priority date	Sep 29, 2017
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A method for fabricating a semiconductor device includes: forming a plurality of bit line structures over a semiconductor substrate; forming a line-type opening between the bit line structures; forming a sacrificial spacer on both sidewalls of the line-type opening; forming a line-type plug filling the line-type opening over the sacrificial spacer; forming a plurality of plug isolation openings that expose the sacrificial spacer by etching a portion of the line-type plug in a direction crossing the bit line structures; forming a plurality of air gaps by removing the exposed sacrificial spacer; removing a remaining line-type plug below the plug isolation openings to form a plurality of island-type plugs; and forming a plug isolation layer inside the plug isolation openings to isolate neighboring island-type plugs from each other.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a plurality of bit line structures over a semiconductor substrate;
forming a line-type opening between the bit line structures;
forming a sacrificial spacer on both sidewalls of the line-type opening;
forming a line-type plug by filling the line-type opening over the sacrificial spacer;
forming a plurality of plug isolation openings that expose the sacrificial spacer by etching a portion of the line-type plug in a direction crossing the bit line structures;
forming a plurality of air gaps by removing the exposed sacrificial spacer;
removing a remaining line-type plug below the plug isolation openings to form a plurality of island-type plugs; and
forming a plug isolation layer inside the plug isolation openings to isolate neighboring island-type plugs from each other.

2. The method of claim 1 , wherein in the forming of the plurality of the air gaps by removing the exposed sacrificial spacer,
each of the air gaps is formed to have a linear shape that is extended in parallel with both sidewalls of each of the bit line structures.

3. The method of claim 1 , wherein the forming of the plug isolation layer inside the plug isolation openings to isolate the neighboring island-type plugs from each other includes:
transforming the air gaps into isolated-type air gaps that are disposed between the bit line structures and the island-type plugs, wherein the isolated-type air gaps are isolated from each other by the plug isolation layer.

4. The method of claim 1 , further comprising, after the forming of the plug isolation layer inside the plug isolation openings to isolate the neighboring island-type plugs from each other:
recessing an upper portion of each of the island-type plugs to form a plug recess portion;
forming a surrounding spacer on a sidewall of the plug recess portion;
forming an ohmic contact layer on a surface of the recessed island-type plug; and
forming a metal plug filling the plug recess portion over the ohmic contact layer.

5. The method of claim 1 , wherein the forming of the plurality of the plug isolation openings that expose the sacrificial spacer by etching the portion of the line-type plug in the direction crossing the bit line structures includes:
forming a plurality of mask layers that are extended in a direction crossing the bit line structures and the line-type plug over the bit line structures and the line-type plug; and
etching the line-type plug by using the mask layer and the bit line structures as etch barriers in a depth that the sacrificial spacer is exposed.

6. The method of claim 1 , wherein the sacrificial spacer includes a material having an etch selectivity with respect to the line-type plug.

7. The method of claim 1 , wherein the sacrificial spacer includes a titanium nitride.

8. The method of claim 1 , wherein the forming of the line-type plug by filling the line-type opening over the sacrificial spacer includes:
forming a polysilicon layer over the bit line structures to fill the line-type opening; and
isolating the polysilicon layer to be exposed at the same level as upper surfaces of the bit line structures.

9. The method of claim 1 , wherein the forming of the plurality of the bit line structures over the semiconductor substrate includes:
forming an inter-layer dielectric layer over the semiconductor substrate;
forming a bit line contact hole by etching the inter-layer dielectric layer;
forming a preliminary plug that fills the bit line contact hole;
sequentially forming a conductive layer and a hard mask layer over the preliminary plug and the inter-layer dielectric layer;
sequentially etching the hard mask layer, the conductive layer, and the preliminary plug to form the bit line structures where a bit line contact plug, a bit line, and a bit line hard mask layer are sequentially stacked; and
forming a bit line spacer on both sidewalls of the bit line, the bit line contact plug, and the bit line hard mask layer.

10. The method of claim 9 , wherein the air gaps are formed between the bit line and the island-type plugs and are extended vertically to be positioned between the island-type plug and the bit line contact plug.

11. A method for fabricating a semiconductor device, comprising:
forming a plurality of bit line structures over a semiconductor substrate;
forming a line-type opening between the bit line structures;
forming a sacrificial spacer on both sidewalls of the line-type opening;
forming a line-type plug by filling the line-type opening between the bit line structures over the sacrificial spacer;
forming a plurality of island-type plugs and a plurality of plug isolation openings by etching the line-type plug in a direction crossing the bit line structures; and
forming a plurality of air gaps by removing the sacrificial spacer exposed by the plug isolation openings, and
forming a plug isolation layer inside the plug isolation openings to isolate neighboring island type plugs from each other.

12. The method of claim 11 , wherein in the forming of the plurality of the air gaps by removing the sacrificial spacer exposed by the plug isolation openings,
each of the air gaps is formed to have a linear shape that is extended in parallel with both sidewalls of each of the bit line structures.

13. The method of claim 11 , wherein the forming of the plug isolation layer inside the plug isolation openings to isolate the neighboring island-type plugs from each other include:
transforming the air gaps into isolated-type air gaps that are disposed between the bit line structures and the island-type plugs, wherein the isolated-type air gaps are isolated from each other by the plug isolation layer.

14. The method of claim 11 , further comprising, after the forming of the plug isolation layer inside the plug isolation openings to isolate the neighboring island-type plugs from each other:
recessing an upper portion of each of the island-type plugs to form a plug recess portion;
forming a surrounding spacer on a sidewall of the plug recess portion;
forming an ohmic contact layer on a surface of the recessed island-type plug; and
forming a metal plug filling the plug recess portion over the ohmic contact layer.

15. The method of claim 11 , wherein the forming of the plurality of the island-type plugs and the plurality of the plug isolation openings by etching the line-type plug in the direction crossing the bit line structures includes:
forming a plurality of mask layers that are extended in a direction crossing the bit line structures and the line-type plug over the bit line structures and the line-type plug; and
etching the line-type plug by using the mask layer and the bit line structures as etch barriers.

16. The method of claim 11 , wherein the sacrificial spacer includes a material having an etch selectivity with respect to the line-type plug.

17. The method of claim 11 , wherein the sacrificial spacer includes a titanium nitride.

18. The method of claim 11 , wherein the forming of the line-type plug by filling the line-type opening over the sacrificial spacer includes:
forming a polysilicon layer over the bit line structures to fill the line-type opening; and
isolating the polysilicon layer to be exposed at the same level as upper surfaces of the bit line structures.

19. The method of claim 11 , wherein the forming of the plurality of the bit line structures over the semiconductor substrate includes:
forming an inter-layer dielectric layer over the

Assignees

• Sk Hynix Inc

Inventors

• Yoon Jae-Man

Classifications

• H01L21/7682 Primary

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic

• H01L21/76805

  Electricity · mapped topic

• H01L27/10888

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic