Semiconductor device having air-gap

Patent metadata

Field	Value
Publication number	US-9824726-B2
Application number	US-201615164442-A
Country	US
Kind code	B2
Filing date	May 25, 2016
Priority date	Mar 17, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a bit line structure extending in a first direction;
an inner bit line spacer extending in the first direction, the inner bit line spacer disposed on a side surface of the bit line structure;
a block bit line spacer extending in the first direction, the block bit line spacer spaced apart from the inner bit line spacer in a second direction perpendicular to the first direction, and a region interposed in the second direction between the block bit line spacer and the inner bit line spacer being unoccupied such that an air-gap exists in the region between the inner bit line spacer and the block bit line spacer,
wherein a profile of a first side surface of the block bit line spacer facing the inner bit line spacer is different from a profile of a second side surface of the block bit line spacer opposite the first side surface of the block bit line spacer.

2. The semiconductor device of claim 1 , wherein the second side surface of the block bit line spacer is parallel to a side surface of the inner bit line spacer facing the first side surface of the block bit line spacer.

3. The semiconductor device of claim 1 , further comprising:
a storage contact plug disposed on the second side surface of the block bit line spacer; and
a plug isolation pattern disposed on the second side surface of the block bit line spacer, the plug isolation pattern aligned with the storage contact plug in the first direction,
wherein a horizontal length of a first part of the block bit line spacer disposed between the air-gap and the storage contact plug in the second direction is greater than a horizontal length of a second part of the block bit line spacer disposed between the air-gap and the plug isolation pattern in the second direction.

4. The semiconductor device of claim 3 , wherein a horizontal length of the air-gap disposed between the inner bit line spacer and the first part of the block bit line spacer in the second direction is smaller than a horizontal length of the air-gap disposed between the inner bit line spacer and the second part of the block bit line spacer in the second direction.

5. The semiconductor device of claim 3 , wherein the horizontal length of the first part of the block bit line spacer in the second direction is smaller than the horizontal length of the air-gap disposed between the inner bit line spacer and the first part of the block bit line spacer in the second direction.

6. The semiconductor device of claim 1 , wherein the bit line structure includes a lower bit line barrier pattern, an upper bit line barrier pattern, a lower bit line electrode, a DC plug, an intermediate bit line pattern, an upper bit line electrode and a bit line capping pattern.

7. The semiconductor device of claim 1 , wherein the block bit line spacer has a planar horizontal upper surface, and a planar horizontal lower surface such that the upper and lower surfaces of the block bit line spacer are parallel.

8. A semiconductor device, comprising:
a bit line structure extending in a first direction;
an inner bit line spacer extending in the first direction, the inner bit line spacer disposed on a side surface of the bit line structure, the inner bit line spacer having an inner side surface facing the bit line structure and an outer side surface opposite the inner side surface; and
a block bit line spacer extending in the first direction,
the block bit line spacer having a first side surface facing the inner bit line spacer in a second direction perpendicular to the first direction and a second side surface opposite the first side surface, and the first side surface of the block bit line spacer being spaced apart from the outer surface of the inner bit line spacer in the second direction, and
wherein an air-gap is present, as extending in the first direction, between the outer side surface of the inner bit line spacer and the first side surface of the block bit line spacer, and
wherein a profile of the first side surface of the block bit line spacer facing the inner bit line spacer is different from a profile of the second side surface of the block bit line spacer opposite the first side surface of the block bit line spacer.

9. The semiconductor device of claim 8 , wherein the second side surface of the block bit line spacer is parallel to a side surface of the inner bit line spacer facing the first side surface of the block bit line spacer.

10. The semiconductor device of claim 8 , further comprising:
a storage contact plug disposed on the second side surface of the block bit line spacer; and
a plug isolation pattern disposed on the second side surface of the block bit line spacer, the plug isolation pattern aligned with the storage contact plug in the first direction,
wherein a horizontal length of a first part of the block bit line spacer disposed between the air-gap and the storage contact plug in the second direction is greater than a horizontal length of a second part of the block bit line spacer disposed between the air-gap and the plug isolation pattern in the second direction.

11. The semiconductor device of claim 10 , wherein a horizontal length of the air-gap disposed between the inner bit line spacer and the first part of the block bit line spacer in the second direction is smaller than a horizontal length of the air-gap disposed between the inner bit line spacer and the second part of the block bit line spacer in the second direction.

12. The semiconductor device of claim 10 , wherein the horizontal length of the first part of the block bit line spacer in the second direction is smaller than the horizontal length of the air-gap disposed between the inner bit line spacer and the first part of the block bit line spacer in the second direction.

13. The semiconductor device of claim 8 , wherein the bit line structure includes a lower bit line barrier pattern, an upper bit line barrier pattern, a lower bit line electrode, a DC plug, an intermediate bit line pattern, an upper bit line electrode and a bit line capping pattern.

14. The semiconductor device of claim 8 , wherein the block bit line spacer has a planar horizontal upper surface, and a planar horizontal lower surface such that the upper and lower surfaces of the block bit line spacer are parallel.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Jung-Hoon
• Kim Dong-Wan
• Lee Ju-Ik

Classifications

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/021 Primary

  of air gaps · CPC title