Interposer and semiconductor package including the same

Patent metadata

Field	Value
Publication number	US-11688656-B2
Application number	US-202017098748-A
Country	US
Kind code	B2
Filing date	Nov 16, 2020
Priority date	Apr 13, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first package substrate;
a first semiconductor chip on the first package substrate;
an interposer substrate comprising a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface;
a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad, the first dam structure including an inner wall defining an opening;
a first molding layer in contact with an outer wall of the first dam structure and including a lower portion extending under the lower surface of the interposer substrate, a middle portion extending along a sidewall of the interposer substrate, and an upper portion contiguous with the middle portion and extending over the upper surface of the interposer substrate; and
a conductive connector in the opening of the first dam structure such that the conductive connector contacts the upper conductive pad and the inner wall of the first dam structure,
wherein an upper surface of the conductive connector is higher than at least one of an upper surface of the first dam structure or an upper surface of the first molding layer,
wherein the first semiconductor chip is provided between the first package substrate and the interposer substrate,
wherein the first dam structure includes a material different from a material of the first molding layer and a material of the conductive connector,
wherein the first dam structure includes an insulating material, and
wherein the upper surface of the first molding layer is coplanar with the upper surface of the first dam structure.

2. The semiconductor package of claim 1 , wherein the first dam structure has a ring shape continuously extending along the edge of the upper conductive pad.

3. The semiconductor package of claim 1 , wherein
the upper conductive pad is one of a plurality of conductive pads,
the first dam structure is one of a plurality of first dam structures spaced apart from each other such that at least a portion the first molding layer is between the plurality of first dam structures, and
wherein each of the first dam structures extends along edges of different upper conductive pads, and
wherein the first molding layer is between the first dam structures.

4. The semiconductor package of claim 1 , wherein a height of the first dam structure is 5 micrometers to 100 micrometers.

5. The semiconductor package of claim 1 , wherein the first dam structure at least partially overlaps the upper conductive pad in a vertical direction.

6. The semiconductor package of claim 1 , further comprising:
a second dam structure on the upper surface of the interposer substrate,
wherein the upper conductive pad is one of a plurality of conductive pads, the first dam structure in one of a plurality of first dam structures, and the plurality of first dam structures are spaced apart from each other, and
wherein each of the first dam structures extends along edges of different upper conductive pads, and
wherein the second dam structure encloses the plurality of first dam structures.

7. The semiconductor package of claim 6 , further comprising:
a trench part in the upper surface of the interposer substrate between the plurality of first dam structures and the second dam structure.

8. The semiconductor package of claim 1 , further comprising:
a second semiconductor chip connected to the interposer substrate through the conductive connector.

9. The semiconductor package of claim 8 , further comprising:
a second molding layer in contact with the second semiconductor chip and the first molding layer.

10. The semiconductor package of claim 1 , further comprising:
a second package substrate connected to the interposer substrate through the conductive connector; and
a second semiconductor chip on the second package substrate.

11. A semiconductor package comprising:
a first package substrate;
a first semiconductor chip on the first package substrate;
an interposer substrate comprising a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and a plurality of lower conductive pads in the lower surface and a plurality of upper conductive pads in the upper surface;
first conductive connectors between the plurality of lower conductive pads and the first package substrate;
a plurality of first dam structures on the upper surface of the interposer substrate and having a ring shape continuously extending along an edge of a corresponding upper conductive pad, of the plurality of upper conductive pads, each of the plurality of first dam structures including an inner wall defining an opening; and
a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with outer walls of the plurality of first dam structures, the first molding layer comprising a first portion above the upper surface of the interposer substrate such that the first portion of the first molding layer is between the plurality of first dam structures and has an upper surface planar to or lower than an upper surface of the ring shape of each of the first dam structure,
wherein the first semiconductor chip is provided between the first package substrate and the interposer substrate,
wherein the plurality of first dam structures includes a material different from a material of the first molding layer and a material of the first conductive connectors, and
wherein the first dam structure includes an insulating material.

12. The semiconductor package of claim 11 , further comprising:
a second conductive connector in contact with the inner wall of one of the plurality of first dam structures and the corresponding upper conductive pad;
a second semiconductor chip on the interposer substrate and connected to the interposer substrate through the second conductive connector; and
a second molding layer covering a side surface of the second semiconductor chip and contacting the first molding layer.

13. The semiconductor package of claim 11 , further comprising:
a second conductive connector in contact with the inner wall of one of the plurality of first dam structures and with the corresponding upper conductive pad;
a second package substrate on the interposer substrate, and connected to the interposer substrate through the second conductive connector; and
a second semiconductor chip on the second package substrate.

14. The semiconductor package of claim 1 , wherein the first dam structure includes a solder resist.

15. The semiconductor package of claim 1 , the first dam structure physically isolates the upper conductive pad from the first molding layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Junyoung
• Baek Hyunggil
• Kim Seunghwan
• Kim Jungjoo
• Park Jongho
• Lee Yongkwan

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title