Localized stress regions for three-dimension chiplet formation

Patent metadata

Field	Value
Publication number	US-11688642-B2
Application number	US-202117486189-A
Country	US
Kind code	B2
Filing date	Sep 27, 2021
Priority date	Jan 26, 2021
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

First claim

What is claimed is:

1. A method, comprising:
providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof;
attaching the first side of the first semiconductor structure to a carrier substrate;
forming a first stress film on a second side of the first semiconductor structure;
patterning the first stress film to form a first patterned stress film with at least one recessed region;
forming a second stress film within the recessed region and on the first patterned stress film;
polishing the second stress film to planarize the second stress film;
separating the carrier substrate from the first semiconductor structure;
cutting the first patterned stress film and the second stress film and the first semiconductor structure to define at least one chiplet; and
bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

2. The method of claim 1 , further comprising removing the first patterned stress film and the second stress film after the at least one chiplet is bonded to the second semiconductor structure.

3. The method of claim 1 , wherein the first semiconductor structure further has a first dielectric layer formed on the second side thereof, and forming a first stress film on a second side of the first semiconductor structure includes forming a first stress film on the first dielectric layer of the first semiconductor structure.

4. The method of claim 3 , wherein the first semiconductor structure further has a first substrate formed on the first dielectric layer, and the method further comprises, prior to forming a first stress film on the first dielectric layer of the first semiconductor structure, removing the first substrate to uncover the first dielectric layer.

5. The method of claim 1 , wherein the first side of the first semiconductor structure is attached to the carrier substrate using an attachment material, and separating the carrier substrate from the first semiconductor structure includes heating the attachment material such that the carrier substrate is separated from the first semiconductor structure.

6. The method of claim 1 , wherein the second stress film is further formed on the first patterned stress film.

7. The method of claim 1 , wherein the first patterned stress film is formed via a mask-based lithography tool, ultraviolet (UV) cross-linking or a direct-write lithography tool.

8. The method of claim 7 , wherein the first patterned stress film is formed via the direct-write lithography tool using a digital light processing (DLP) chip, a grating light valve or a laser galvanometer.

Assignees

• Tokyo Electron Ltd

Inventors

• Devilliers Anton J
• Fulford Daniel J
• Schepis Anthony R
• Gardner Mark I
• Fulford H Jim

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title