Memory device including multiple select gates and different bias conditions

Patent metadata

Field	Value
Publication number	US-9728266-B1
Application number	US-201615205574-A
Country	US
Kind code	B1
Filing date	Jul 8, 2016
Priority date	Jul 8, 2016
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

First claim

What is claimed is:

1. An apparatus comprising:
a conductive line;
a first memory cell string and a second memory cell string; and
a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;
a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;
a first select line to provide a first voltage to the first select gate during an operation of the apparatus;
a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;
a third select line to provide a third voltage to the third select gate during the operation;
a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values;
first control lines coupled to the first memory cell string; and
second control lines coupled to the second memory cell string, the second control lines being different from the first control lines, and the operation includes one of an operation of storing information in a memory cell of the first memory cell string and an operation of reading information from a memory cell of the first memory cell string.

2. An apparatus comprising:
a conductive line;
a first memory cell string and a second memory cell string; and
a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;
a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;
a first select line to provide a first voltage to the first select gate during an operation of the apparatus;
a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;
a third select line to provide a third voltage to the third select gate during the operation; and
a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values, wherein:
the first select line is to provide a fifth voltage to the first select gate during an additional operation of the apparatus;
the second select line is to provide a sixth voltage to the second select gate during the additional operation, the fifth and sixth voltages having a same value;
the third select line is to provide a seventh voltage to the third select gate during the additional operation; and
the fourth select line is to provide an eighth voltage to the fourth select gate during the additional operation, the seventh and eighth voltages having a same value, and the fifth and seventh voltages having different values.

3. An apparatus comprising:
a conductive line;
a first memory cell string and a second memory cell string; and
a first select Rate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;
a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;
a first select line to provide a first voltage to the first select gate during an operation of the apparatus;
a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;
a third select line to provide a third voltage to the third select gate during the operation;
a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values; and
a substrate, wherein the first memory cell string is located between the substrate and the first and second select gates.

4. The apparatus of claim 3 , further comprising control lines shared by the first and second memory cell strings, and the operation includes one of an operation of storing information in a memory cell of the first memory cell string and an operation of reading information from a memory cell of the memory cell string.

5. The apparatus of claim 3 , wherein the first and third voltages are provided by a same signal of the apparatus.

6. The apparatus of claim 3 , wherein the first and third voltages are provided by different signals of the apparatus.

7. The apparatus of claim 3 , wherein each of the first, second, third, and fourth select gates includes a charge storage element.

8. The apparatus of claim 3 , wherein each of the first and second memory cell strings includes a memory cell, the memory cell including a floating-gate memory cell structure.

9. The apparatus of claim 3 , wherein each of the first and second memory cell strings includes a memory cell, the memory cell including a charge-trap memory cell structure.

10. An apparatus comprising:
a conductive line;
a first memory cell string and a second memory cell string; and
a first select gate and a second select gate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;
a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being located in the first level, the fourth select gate being located in the second level;
a first select line to provide a first voltage to the first select gate during an operation of the apparatus;
a second select line to provide a second voltage to the second select gate during the operation, the first and second voltages having a same value;
a third select line to provide a third voltage to the third select gate during the operation; and
a fourth select line to provide a fourth voltage to the fourth select gate during the operation, the third and fourth voltages having different values, wherein the apparatus comprises a memory device, the memory device including a first block of memory cells and a second block of memory cells, the first memory string included in the first block of memory cells, the second memory cell string included in the second block of memory cells and wherein the third voltage has a value greater than a value of the fourth voltage during the operation if the second block of memory cells is a deselected block.

11. An apparatus comprising:
a conductive line;
a first memory cell string and a second memory cell string; and
a first select Rate and a second select Rate coupled in series between the conductive line and the first memory cell string, the first select gate being located in a first level of the apparatus, the second gate being located in a second level of the apparatus;
a third select gate and a fourth select gate coupled in series between the conductive line and the second memory cell string, the third select gate being lo

Assignees

• Micron Technology Inc

Inventors

• Goda Akira
• Liu Haitao
• Lee Changhyun

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title