And-type SGVC architecture for 3D NAND flash

Patent metadata

Field	Value
Publication number	US-9530503-B2
Application number	US-201514723321-A
Country	US
Kind code	B2
Filing date	May 27, 2015
Priority date	Feb 19, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings. The memory device includes control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.

First claim

What is claimed is:

1. A memory device including a plurality of strings of memory cells, comprising:
a plurality of stacks of conductive strips, including first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings, the strings of memory cells being disposed vertically between stacks of conductive strips in the plurality of stacks; and
control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.

2. The memory device of claim 1 , wherein the second upper strips are disposed between the upper strips and the intermediate strips.

3. The memory device of claim 1 , wherein the plurality of strings of memory cells includes multiple sets of strings, comprising:
first string select structures, each of the first string select structures coupled to first string select lines in a respective set of strings in the multiple sets of strings; and
second string select structures, each of the second string select structures coupled to a respective second string select line in each set of strings in the multiple sets of strings,
wherein a combination of a first string select structure in the first string select structures and a second string select structure in the second string select structures selects a string in the multiple sets of strings.

4. The memory device of claim 3 , wherein each of the second string select structures is coupled to multiple strings in respective sets of strings in the multiple sets of strings.

5. The memory device of claim 1 , wherein the plurality of strings of memory cells includes K sets of N strings, comprising:
K first string select structures, each of the K first string select structures coupled to N first string select lines in a respective set in the K sets of N strings; and
N second string select structures, each of the N second string select structures coupled to a respective second string select line in each set of strings in the K sets of N strings,
wherein a combination of a first string select structure in the K first string select structures and a second string select structure in the N second string select structures selects a string in the K sets of N strings.

6. The memory device of claim 5 , wherein:
the K first string select structures include K first linking elements in a first patterned conductor layer over the plurality of stacks of conductive strips, each of the K first linking elements connecting N first string select lines in a respective set in the K sets of N strings; and
the N second string select structures include N second linking elements in the first patterned conductor layer, each of the N second linking elements connecting a respective second string select line in each set in the K sets of N strings.

7. The memory device of claim 6 , wherein:
the K first string select structures include first interlayer connectors connecting K first patterned conductor lines to the K first linking elements respectively;
the N second string select structures include second interlayer connectors connecting N second patterned conductor lines to the N second linking elements respectively; and
the K first patterned conductor lines and the N second patterned conductor lines are disposed in a patterned conductor layer or layers higher than the first patterned conductor layer, connecting the K sets of N strings to a string decoder.

8. The memory device of claim 1 , the control circuitry configured to deselect a particular string in the plurality of strings by applying a turn-off voltage to one or both of a first string select line in the first string select lines coupled to the particular string, and a second string select line in the second string select lines coupled to the particular string.

9. The memory device of claim 1 , wherein the second turn-on voltage is lower than the first turn-on voltage.

10. The memory device of claim 1 , wherein the plurality of stacks includes even stacks and odd stacks, comprising:
data storage structures on sidewalls of corresponding even stacks and odd stacks of conductive strips in the plurality of stacks; and
semiconductor films disposed on the data storage structures on the sidewalls of the corresponding even stacks and odd stacks, and connected to form a current path from an upper end to a lower end of the semiconductor films on the corresponding even stacks, and from a lower end to an upper end of the semiconductor films on the corresponding odd stacks.

11. The memory device of claim 10 , wherein the even stacks of conductive strips include the first upper strips configured as the first string select lines and the second upper strips configured as the second string select lines.

12. The memory device of claim 10 , wherein the odd stacks of conductive strips include upper strips configured as ground select lines.

13. The memory device of claim 10 , wherein at least one of the even stacks and odd stacks of conductive strips include bottom strips configured as assist gates disposed below the intermediate strips.

14. The memory device of claim 1 , comprising:
data storage structures on sidewalls of stacks of conductive strips in the plurality of stacks; and
semiconductor films disposed on the data storage structures on the sidewalls of the stacks, forming a current path from an upper end to a lower end of the semiconductor films between the stacks.

15. The memory device of claim 1 , the stacks including bottom strips configured as ground select lines disposed below the intermediate strips.

16. A method of operating a memory device including a plurality of strings of memory cells, wherein a plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings, the strings of memory cells being disposed vertically between stacks of conductive strips in the plurality of stacks, comprising:
selecting a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.

17. The method of claim 16 , wherein the second turn-on voltage is lower than the first turn-on voltage.

18. The method of claim 16 , comprising:
deselecting a particular string in the plurality of strings by applying a turn-off voltage to one or both of a first string select line in the first string select lines coupled to the particular string, and a second string select line in the second string select lines coupled to the particular string.

19. The method of claim 16 , wherein a given string in the strings of memory cells has a first end and a second end, the first end being proximate to

Assignees

• Macronix Int Co Ltd

Inventors

• Chang Kuo-Pin
• Lue Hang-Ting

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title