Program verify word line ramping delay for lower current consumption mode
US-2024395343-A1 · Nov 28, 2024 · US
US8964474B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8964474-B2 |
| Application number | US-201213524872-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 15, 2012 |
| Priority date | Jun 15, 2012 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.
Opening claim text (preview).
What is claimed is: 1. An apparatus, comprising: a plurality of stacked arrays, including: memory strings of a first array of memory cell strings coupled between a first source and a first data line; memory strings of a second array of memory cell strings coupled between a second source and a second data line; a shared data detector coupled to both the first data line and the second data line; and a first switch coupled between the first data line and the shared data dete…
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