Architecture for 3-D NAND memory

US8964474B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8964474-B2
Application numberUS-201213524872-A
CountryUS
Kind codeB2
Filing dateJun 15, 2012
Priority dateJun 15, 2012
Publication dateFeb 24, 2015
Grant dateFeb 24, 2015

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Abstract

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Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

First claim

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What is claimed is: 1. An apparatus, comprising: a plurality of stacked arrays, including: memory strings of a first array of memory cell strings coupled between a first source and a first data line; memory strings of a second array of memory cell strings coupled between a second source and a second data line; a shared data detector coupled to both the first data line and the second data line; and a first switch coupled between the first data line and the shared data dete…

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What does patent US8964474B2 cover?
Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.
Who is the assignee on this patent?
Morooka Midori, Tanaka Tomoharu, Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification G11C16/0483. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).