Operating method of a nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-9620219-B2
Application number	US-201614997730-A
Country	US
Kind code	B2
Filing date	Jan 18, 2016
Priority date	Jan 21, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device, comprising:
first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and
second programming the target transistor of the cell string, wherein the target transistor has a second threshold voltage distribution after the second programming,
wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution,
wherein the second programming is not performed when an upper limit of the first threshold voltage distribution is lower than a verify voltage.

2. The method of claim 1 , wherein the second programming is performed when the upper limit of the first threshold voltage distribution is higher than the verify voltage, and an upper limit of the second threshold voltage distribution is lower than the verify voltage after the second programming.

3. The method of claim 1 , wherein the target transistor is a ground select transistor or a memory cell.

4. The method of claim 1 , wherein the second programming comprises:
applying a boosted voltage to a drain of the target transistor;
applying a common source line voltage to a source of the target transistor; and
applying a negative voltage to a gate of the target transistor.

5. The method of claim 1 , wherein the second programming is a hot hole injection operation.

6. The method of claim 1 , wherein the first programming comprises:
supplying a low voltage to a channel of the target transistor; and
supplying a high voltage to a gate of the target transistor.

7. A method of operating a nonvolatile memory device including a plurality of strings, each string including a plurality of sting selection transistors, a plurality of memory cells, and a plurality of ground selection transistors sequentially stacked in a direction perpendicular to a surface of a substrate on which the cell string is disposed, the method comprising:
programming a ground selection transistor of a selected cell string, wherein the programming comprises:
applying a boosted voltage to a drain of the ground selection transistor of the selected string;
applying a common source line voltage to a source of the ground selection transistor of the selected string; and
applying a negative voltage to a gate of the ground selection transistor of the selected string,
wherein a width of threshold voltage distribution of the ground selection transistor of the selected string is decreased.

8. The method of claim 7 , wherein the boosting voltage is generated by:
initially turning on the string selection transistors of the selected string;
supplying a bit line voltage to a bit line connected to the selected string;
turning off the string selection transistors of the selected string; and
applying a pass voltage to the memory cells of the selected string.

9. The method of claim 8 , wherein a difference between the boost voltage and the negative voltage causes a hot hole at the ground selection transistor of the selected string.

10. The method of claim 8 , wherein the bit line voltage is a low voltage, the common source line voltage is a low voltage, the turned off string selection transistors are applied with a high voltage, and an unselected ground selection transistor is applied with a high voltage.

11. The method of claim 7 , wherein the string selection transistors, the memory cells and the ground selection transistors of the selected string are charge trap flash cells.

12. The method of claim 11 , wherein the program inhibiting comprises:
turning on the string selection transistors of the unselected string;
supplying a bit line voltage to a bit line connected to the unselected string, wherein the bit line voltage is a low voltage; and
applying a pass voltage to the memory cells of the unselected string.

13. The method of claim 12 , wherein the string selection transistors, the memory cells and the ground selection transistors of the unselected string are charge trap flash cells.

14. The method of claim 7 , further comprising:
inhibiting programming of a ground selection transistor of an unselected string while the ground selection transistor of the selected string is programmed.

15. An operation method of a nonvolatile memory device including a plurality of cell transistors comprising:
performing a first program operation to increase threshold voltages of the cell transistors; and
performing a second program operation to decrease threshold voltages of cell transistors having threshold voltages higher than a verify voltage among the cell transistors,
wherein the performing the second program operation comprises:
performing a verify operation with respect to the cell transistors using the verify voltage;
inhibiting a program of first cell transistors having threshold voltages lower than the verify voltage among the cell transistors according to a result of the verify operation;
allowing a program of second cell transistors having threshold voltages higher than the verify voltage among the cell transistors according to a result of the verify operation; and
supplying a negative voltage to control gates of the cell transistors.

16. The operation method of claim 15 , wherein until threshold voltages of the second cell transistors become lower than the verify voltage, the inhibiting a program of the first cell transistors, the allowing a program of the second cell transistors and the supplying the negative voltage are repeatedly performed.

17. The operation method of claim 15 , wherein the inhibiting a program of the first cell transistors, the allowing a program of the second cell transistors and the supplying the negative voltage are repeated predetermined number of times.

18. The operation method of claim 15 , wherein a program of the first cell transistors is inhibited by supplying a low voltage to drains and sources of the first cell transistors.

19. The operation method of claim 15 , wherein a program of the second cell transistors is allowed by floating drains of the second cell transistors, boosting the floated drains of the second cell transistors to a high voltage and supplying a low voltage to sources of the second cell transistors.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Wandong

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3404 Primary

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/30

  Power supply circuits · CPC title