Method and apparatus of processor wafer bonding for wafer-scale integrated supercomputer

Patent metadata

Field	Value
Publication number	US-11651973-B2
Application number	US-202016869744-A
Country	US
Kind code	B2
Filing date	May 8, 2020
Priority date	May 8, 2020
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A method and apparatus for bonding a processor wafer with a microchannel wafer/glass manifold to form a bonded wafer structure are provided. A glass fixture is also provided for protecting C4 solder bumps on chips disposed on the processor wafer. When the glass fixture is positioned on the processor wafer, posts extending from the glass fixture contact corresponding regions on the processor wafer devoid of C4 solder bumps, so that the glass fixture protects the C4 solder bumps during wafer bonding. The method involves positioning the processor wafer/glass fixture and the microchannel wafer/glass manifold in a metal fixture having one or more alignment structures adapted to engage corresponding alignment elements formed in the processor wafer, glass fixture and/or glass manifold. The metal fixture secures the wafer components in place and, after melting solder pellets disposed between the processor wafer/glass fixture and microchannel wafer/glass manifold, a bonded wafer structure is formed.

First claim

What is claimed is:

1. A method for forming a bonded wafer structure, the method comprising:
providing a processor wafer having a top surface and a bottom surface and comprising a plurality of chips disposed on the top surface and a first metal layer disposed on the bottom surface, wherein each at least a subset of the plurality of chips comprises a plurality of uniformly distributed C4 solder bumps having a first height and a plurality of regions devoid of any C4 solder bumps;
providing a glass manifold assembly, the glass manifold assembly comprising a microchannel cooling wafer having a top surface, including a plurality of etched channels therein, and a bottom surface, including a second metal layer disposed thereon, wherein the top surface of the microchannel cooling wafer is contacted by a glass manifold;
providing a glass fixture having top and bottom surfaces with a plurality of posts extending from the top surface to a second height, wherein the second height is greater than the first height, and wherein the plurality of posts is in registration with the plurality of regions devoid of any C4 solder bumps;
positioning the glass fixture onto the top surface of the processor wafer, wherein the plurality of posts contacts the plurality of regions devoid of any C4 solder bumps, the glass fixture and the processor wafer together forming a wafer assembly;
positioning the wafer assembly on a metal fixture having at least one alignment element, where the glass fixture contacts the metal fixture;
applying a uniformly distributed plurality of solder pellets on the first metal layer;
positioning the glass manifold assembly on the wafer assembly so that the second metal layer contacts the plurality of uniformly distributed solder pellets on the first metal layer;
melting the plurality of solder pellets to form a bonded solder layer, the first and second metal layers being attached by the bonded solder layer to thereby form the bonded wafer structure.

2. The method according to claim 1 , wherein at least a subset of the plurality of chips disposed on the top surface of the processor wafer are connected together using wiring layers formed in the processor wafer.

3. The method according to claim 1 , wherein each of the processor wafer and the microchannel cooling wafer has a first diameter, and the glass manifold has a second diameter, and wherein the first diameter is less than the second diameter.

4. The method according to claim 1 , further comprising:
removing the bonded wafer structure from the metal fixture; and
removing the glass fixture from the bonded wafer structure.

5. The method according to claim 1 , wherein each of the plurality of C4 solder bumps has a diameter of at least 0.005 millimeter.

6. The method according to claim 1 , wherein each of the plurality of C4 solder bumps has a diameter of about 0.070 millimeter.

7. The method according to claim 1 , wherein after melting, the plurality of solder pellets forms a layer having a substantially uniform thickness from about 10 to 1,000 microns.

8. The method according to claim 7 , wherein the layer formed by the solder pellets has a uniform thickness from about 100 to 250 microns.

9. The method according to claim 1 , wherein at least one of the first and second metal layers comprises a multi-layer structure.

10. The method according to claim 9 , wherein the multi-layer structure comprises one of layers of gold (Au)/nickel (Ni)/copper (Cu)/titanium (Ti), Au/Ni/Ti, Au/palladium (Pd)/Ti, Au/Pd/Ni/Ti, Pd/Ni/Cu/Ti, and Pd/Ni/Ti.

11. The method according to claim 10 , wherein in the multi-layer structure, the layers of Au, Pd and Ti each have a thickness from about 0.03 to 0.2 μm, the layer of Ni has a thickness from about 0.1 to 1 μm, and the layer of Cu has a thickness from about 0.2 to 2 μm.

12. The method according to claim 1 , wherein melting the plurality of solder pellets comprises:
using a formic acid and nitrogen environment during heating, before the solder pellets melt, to remove surface oxide layers from the solder pellets; and
applying a vacuum as the solder pellets are melting to thereby reduce voids in the bonded solder layer.

13. The method according to claim 1 , wherein after melting, the plurality of solder pellets forms a substantially uniform layer having voids less than 9 millimeters.

14. The method according to claim 1 , wherein at least one of the processor wafer and the glass fixture comprises at least one alignment element formed in a periphery of the respective processor wafer and glass fixture, and wherein positioning the wafer assembly on the metal fixture comprises aligning the alignment elements of the processor wafer and the glass fixture with the alignment element of the metal fixture.

15. The method according to claim 1 , wherein the glass manifold assembly comprises at least one alignment element formed in a periphery of the glass manifold, and wherein positioning the glass manifold assembly on the wafer assembly comprises aligning the alignment elements of the glass manifold and the metal fixture.

Assignees

• IBM

Inventors

• Nah Jae-Woong
• Colgan Evan
• Kuder Ii Robert P
• Speidell James L
• Webb Bucknell C

Classifications

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/0428 Primary

  Apparatus for mechanical treatment or grinding or cutting · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/01204

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title